BK Precision 2560B Series, Руководство пользователя

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Serial Trigger and Decode
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Function Menu Settings Description
CS Type
˜CS Low voltage level of CS signal is available
CS High voltage level of CS signal is available
CLK Timeout
If the time between two edges of the clock signal is less than (or equal to)
the value of timeout, the signal between the two edges is treated as a frame.
The range of clock timeout is 100 ns - 5 ms.
This setting is suitable for case where the CS signal is not connected, or the
number of oscilloscope channels is insufficient (such as 2-channel
oscilloscopes).
Table 10.1 CS Type Parameters
Example
Connect the data, CLK and ˜CS signals of a SPI bus respectively to C1, C2, and C3. Data width = 8-bit, Bit order =
MSB, CS polarity = CS, and 12 data bytes are transmitted in one frame.
In the SPI trigger signal menu, set the source and threshold of CLK, MISO and CS signals, then copy the trigger settings
to decoding. Adjust the timebase, so that the falling edge of the CS signal is shown in the display:
Figure 10.11 Example