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4.13
Slave CPU
The Slave CPU (BRD86SCPU) provides the interfacing signals and
I/O’s required to allow the FACP
to connect / communicate to a variety of termination boards.
A single chip micro controller U7 controls all operations of the FACP Slave CPU. This device contains
the control program within Read Only Memory (ROM).
Automatic Termination Board Sensing
A unique feature of the Slave CPU is its ability to automatically sense the type of board it is connected
to without the user having to configure the board to suit.
Connections
CN2
To Loop Termination Board
CN3
To Main Control Board
BRD86SCB3-
J
T
A
G
DEBUG
COMMS
Q2
R25
R6
C1
C36
C13
C6
C2
C34
C14
C
1
0
C15
C37
C11
C16
C17
C18
C5
C19
C20
C21
C23
C3
C31
C8
C32
C9
C4
C33
C27
C7
C35
C12
CN2
C
N
1
D1
U2
LK1
Q1
R4
R1
R14
R8
R7
R13
R11
R5
R2
R10
R12
R24
RN1
T
P
2
TP5
T
P
3
T
P
4
TP1
U7
U6
U3
U1
U5
U4
X1
R26
R27
D2
D3
CN3
C N 4
Figure 18: Slave CPU Board
Содержание FireFinder PLUS
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