AMD ElanSC310, Руководство пользователя, Страница: 96 / 124

Date: March 29, 1996 Sheet 3 of 23
Size Document Number REV
B ElanSC300/310 Evaluation Board 2.2
Title
Debug Headers
AMD Proprietary/All Rights Reserved
(800) 222-9323
Austin, Texas 78741
5204 E. Ben White Blvd.
(C) Advanced Micro Devices, Inc.
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P3
10th Center 30x2 Berg
AMP 3-102977-0
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P1
10th Center 30x2 Berg
AMP 3-102977-0
MWE#
RAS0#
CAS0L#
CAS1L#
D11
D13
D15
SA15
SA17
SA19
SA21
SA23 GND
RAS1#
CAS0H#
CAS1H#
D10
D12
D14
SA13
SA14
SA16
SA18
SA20
SA22
GND
WP2
VPP2
BVD11
WP1
BVD21
2ICRST
ISA24
MCE1#
REG1#
CD1#
MCE22#
CD2#
GND
BL1#
BL3#
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
VPP1
BVD12
BVD22
BL2#
BL4#
1ICRST
ICDIR
ISA25
MCE12#
RDY1#
WAIT#
MCE2#
REG2#
RDY2#
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
GND
PMC1
DSOE#
DSMA8
DSMA10
DSMA12
DSMA14
GND
LVDD#
SBHE#
’A12(BALE)’
’CPURDY#(LMEG#)’
’A23(LA23)’
’A21(LA21)’
’A19(LA19)’
’A17(LA17)’
GND
’IORESET#’
’DACK1#’
SPKER
PMC0
LD1
RESIN#
DSCE#
DSMA9
DSMA11
DSMA13
DSMD0
VCC1
XIORESET#
’LDEV#(RSVD)’
’A22(LA22)’
’A20(LA20)’
’A18(LA18)’
DRQ2
TC
SDRDH
ROMCS#
D0
D2
D4
D6
D8
GND
’DRQ2[TDO]’
’TC[TMS]’
’ENDIRH’
’ENDIRH’
AEN
PCLK
SDRDL
DOSCS#
D1
D3
D5
D7
D9
GND
’SYSCLK[XTCLK]’
’AEN[TDI]’
’ENDIRL’
SA[0..12]
D[0..15]
SA[13..23]
GND
IOR#
SA8
SA10
SA12
SA[0..12]
D[0..15]
SA[13..23]
EMEMR#
ERESDRV SDEN#
IOW#
SA7
SA9
SA11
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10th Center 30x2 Berg
AMP 3-102977-0
EMEMW#
GND
R225
1M
DSMA1
DSMA3
DSMA5
DSMA7
DSMD1
DSMD3
DSMA[0..14]
DSMD[0..7]
GND
DSMA3
’A16(DACKO#)’
’A14(DACK7#)’
’CPUCLK(PULLUP)’
’PULLUP(IRQ7)’
’LRDY#(DRQ6)’
’BHE#(IRQ9)’
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P4
10th Center 30x2 Berg
AMP 3-102977-0
DSMA0
DSMA2
DSMA4
DSMA6
DSMD2
DSMD4
’A15(DACK3#)’
’A13(DACK6#)’
’CPURST(RSVD)’
’RSVD(PULLUP)’
’BLE#(IRQ11)’
’W/R#(DRQ7)’
DSMA[0..14]
DSMD[0..7]
GND
R224
1M
VCC1
DSMA0
IOCHRDY
PGPC
PGPA
LD3
LD0
CP21
PIRQ0
PMC3
DSMD6
LVEE#
’D/C#(DRQ0)’
’DRQ1’
’IOICHCHK#’
’PULLUP(IRQ10)’
’IRQ15’
’PGP2’
’PGP0’
’PIRQ0(IRQ3)’
’IRQ4’
’DRQ5’
’IRQ12’
’PULLUP’
’PGP3’
’PGP1’
PMC4
PGPD
PGPB
LPH#
LD2
M1
FRM1
CP11
DSWE#
DSMD5
DSMD7
EPIRQ1
’M/IO#(DRQ3)’
’ADS#(OWS#)’
’PULLDN(IRQ5)’
’PIR1(IRQ6)’
PE
A20GATE
PMC2
ERR#
ACK#
8042CS#
SLCTIN#
PPDWE#
MEMR#
MEMW#
SA1
SA3
SA5
MEMR#
MEMW#
’8042CS#[XTDAT]’
’PPDWE#[PPDSC#]’
BUSY
INIT#
RC#
DACK2#
AFDT#
STRB#
SLCT
PPOEN#
SA0
SA2
SA4
SA6
’DACK2#[TCK]’
’AFDT#[X14OUT]’
ACIN
SOUT
DTR#
DSR#
SIN
GND
RESUME#
’DTR#/CFG1’
’SUS#/RES#’
GND
’RTS#/CFG0’
SMI
RTS#
CTS#
DCD#
RI#
MCS16#
JTAGEN
EIRQ1
GND
’IRQ1’
IOCS16#
IRQ14
GND
ELAN Signal Headers
Note:
ElanSC300 Chip/schematic signal name
’ElanSC310 Chip signal name’