AMD ElanSC310, Руководство пользователя, Страница: 94 / 124

Date: March 29, 1996 Sheet 1 of 23
Size Document Number REV
B ElanSC300/310 Evaluation Board 2.2
Title
ElanSC300/310 208-Pin QFP Chip
AMD Proprietary/All Rights Reserved
(800) 222-9323
Austin, Texas 78741
5204 E. Ben White Blvd.
(C) Advanced Micro Devices, Inc.
|LINK
p 2
p 3 |fsocket.sch
p 4
p 5
p 6
p 7
p 8
p 9
p 10
p 11
p 12
p 13
p 14
|header.sch
|misc.sch
|33opt.sch
|dram.sch
|sram.sch
|bufrom.sch
|keybrd.sch
|biosdos.sch
|pcmbufct.sch
|pcmbcon.sch
|pcmnbcon.sch
|cgavideo.sch
SMI
ACIN
PMC0
PMC1
PMC2
PMC4
PGPA
LPH#
JTAGEN
RESIN#
PMC3
LF2
LF3
RESUME#
’SUS#/RES#’
VCCEL5
VCCELSYS
VCCELMEM
VCCELSY2
VCCSY253
1
2
JP6
HEADER 2
’X1OUT[BAUD_OUT]’
’IORESET#’
VCCMEM53
1
2
JP4
HEADER 2
1
2
JP5
HEADER 2
VCC5
VCCEL1
32KOUT
SPKER
LF1
LF4
1
2
JP3
HEADER 2
32KINR
VCC1
1
2
JP19
HEADER 2
XIORESET#
14MOUT
VCCEL1
PCLK
PIRQ0
DACK2#
ELPCLK
OVCC3
L3
47uH
1
2
JP2
HEADER 2
GND
R379
10
C229
33uF TANT
EIRQ1
EPIRQ1
R1 33
VCCSYS5
ELPCLK ’SYSCLK[XTCLK]’
’DACK2#[TCK]’
VCCEL3
VCCEL5
VCCELSYS
VCCELMEM
VCCELSY2
VCCELA
SYSCLK
45
SA0
74
SA1
73
SA2
72
SA3
71
SA4
70
SA5
69
SA6
67
SA7
66
SA8
64
SA9
63
SA10
62
SA11
61
SA12
60
D0
42
D1
41
D2
40
D3
39
D4
38
D5
37
D6
36
D7
34
D8
32
D9
31
D10
30
D11
29
D12
28
D13
27
D14
26
D15
25
M
A
0
/
S
A
1
4
2
4
M
A
1
/
S
A
1
5
2
1
M
A
2
/
S
A
1
6
1
9
M
A
3
/
S
A
1
7
1
8
M
A
4
/
S
A
1
8
1
7
M
A
5
/
S
A
1
9
1
6
M
A
6
/
S
A
2
0
1
5
M
A
7
/
S
A
2
1
1
4
M
A
8
/
S
A
2
2
1
3
M
A
9
/
S
A
2
3
1
1
M
A
1
0
/
S
A
1
3
1
0
CAS1H#(SRCS1#)
5
CAS1L#(SRCS0#)
4
CAS0H#(SRCS3#)
7
CAS0L#(SRCS2#)
6
MWE#
8
RAS1#
3
RAS0#
2
IRQ1
195
PIRQ0(IRQ3)
194
PIRQ1(IRQ6)
193
DACK2#(TCLK)
46
DRQ2(TDO)
76
AEN(TD)
47
TC(TMS)
49
SDWRTH
51
SDWRTL
50
IOR#
54
IOW#
55
MEMR#
56
MEMW#
57
DBUFOE#
59
RSTDRV
58
IOCHRDY
192
A
C
I
N
1
0
1
E
X
T
S
M
I
#
1
0
2
R
E
S
U
M
E
#
1
0
3
P
M
C
0
1
3
7
P
M
C
1
1
3
8
P
M
C
2
7
7
P
M
C
3
1
8
5
P
G
P
0
1
8
9
P
G
P
1
1
8
8
P
G
P
2
1
8
7
P
G
P
3
1
8
6
BL1#
106
BL2#
107
BL3#
108
BL4#
109
L
P
H
#
1
9
0
G
N
D
1
G
N
D
1
0
4
G
N
D
1
5
7
G
N
D
1
0
5
G
N
D
1
2
1
G
N
D
1
9
1
G
N
D
1
5
6
G
N
D
2
0
G
N
D
3
3
G
N
D
5
3
G
N
D
6
8
SBHE(LCDDL1)
143
IOCS16#(LCDDL0)
196
MCS16#(LCDDL1)
197
IRQ14(LCDDL1)
198
L
V
D
D
#
(
B
A
L
E
)
1
4
5
L
V
E
E
#
(
I
R
Q
1
5
)
1
8
2
F
R
M
/
V
D
R
V
(
I
R
Q
1
2
)
1
8
1
C
P
1
/
H
D
R
V
(
P
R
E
Q
/
I
1
7
8
C
P
2
/
V
D
O
(
B
U
S
Y
#
/
I
1
7
9
M
(
I
R
Q
4
)
1
7
3
L
C
D
D
0
/
I
(
D
R
Q
1
)
1
7
4
L
C
D
D
1
/
R
(
D
A
C
K
5
#
)
1
4
4
L
C
D
D
2
/
G
(
D
R
Q
5
)
1
7
5
L
C
D
D
3
/
B
(
I
O
C
H
C
H
K
1
7
7
D
S
C
E
#
(
D
A
C
K
1
#
)
1
4
6
D
S
O
E
#
(
C
P
U
R
D
Y
#
/
L
1
4
7
D
S
W
E
#
(
P
U
L
L
U
P
)
1
8
3
D
S
M
A
0
1
6
5
D
S
M
A
1
(
N
A
#
/
I
R
Q
7
)
1
6
4
D
S
M
A
2
(
C
P
U
R
S
T
)
1
6
3
D
S
M
A
3
(
C
P
U
C
L
K
)
1
6
2
D
S
M
A
4
(
A
1
3
/
D
A
C
K
6
1
6
1
D
S
M
A
5
(
A
1
4
/
D
A
C
K
7
1
6
0
D
S
M
A
6
(
A
1
5
/
D
A
C
K
3
1
5
9
D
S
M
A
7
(
A
1
6
/
D
A
C
K
0
1
5
8
D
S
M
A
8
(
A
1
7
/
L
A
1
7
)
1
5
5
D
S
M
A
9
(
A
1
8
/
L
A
1
8
)
1
5
4
D
S
M
A
1
0
(
A
1
9
/
L
A
1
9
1
5
3
D
S
M
A
1
1
(
A
2
0
/
L
A
2
0
1
5
2
D
S
M
A
1
2
(
A
2
1
/
L
A
2
1
1
5
1
D
S
M
A
1
3
(
A
2
2
/
L
A
2
2
1
5
0
D
S
M
A
1
4
(
A
2
3
/
L
A
2
3
1
4
9
D
S
M
D
0
(
L
D
E
V
#
/
R
E
F
1
4
8
D
S
M
D
1
(
L
R
D
Y
#
/
D
R
Q
1
6
6
D
S
M
D
2
(
B
L
E
#
/
I
R
Q
1
1
6
7
D
S
M
D
3
(
B
H
E
#
/
I
R
Q
9
1
6
8
D
S
M
D
4
(
W
_
R
#
/
D
R
Q
7
1
6
9
D
S
M
D
5
(
M
_
I
O
/
D
R
Q
3
1
7
0
D
S
M
D
6
(
D
_
C
#
/
D
R
Q
0
1
7
1
D
S
M
D
7
(
A
D
S
#
/
0
W
S
#
1
7
2
DOSCS#
43
ROMCS#
44
A
2
0
G
A
T
E
7
9
R
C
#
7
8
8
0
4
2
C
S
#
7
5
RIN#
100
SIN
99
DCD#
98
DSR#
97
CTS#
96
SOUT
94
RTS#
93
DTR#
92
PPOEN#
91
PPDWE#(PPDCS#)
90
INIT#
89
ACK#
88
SLCTIN#
84
ERROR#
86
BUSY
85
SLCT
87
STRB#
83
PE
82
AFDT#
80
CA25
136
CA24
134
BVD2-B
119
BVD1-B
120
WP-B
118
RDY-B#
117
CD-B#
116
RST-B
127
REG-B#
126
VPP-B
125
MCEL-B#
123
MCEH-B#
124
ICDIR
122
WAIT-AB#
115
BVD2-A
113
BVD1-A
114
WP-A
112
RDY-A#
111
CD-A#
110
RST-A
133
REG-A#
132
VPP-A
131
MCEL-A#
129
MCEH-A#
130
G
N
D
2
0
8
G
N
D
5
2
V
C
C
S
Y
S
4
8
V
C
C
S
Y
S
6
5
V
C
C
2
3
V
C
C
M
E
M
9
V
C
C
M
E
M
2
2
V
C
C
M
E
M
3
5
V
C
C
8
1
V
C
C
S
Y
S
2
1
4
2
V
C
C
5
9
5
V
C
C
1
3
5
V
C
C
1
1
7
6
V
C
C
5
1
2
8
V
C
C
1
8
0
A
V
C
C
2
0
3
S
P
K
R
1
3
9
X
I
O
R
E
S
E
T
#
1
4
0
L
F
4
2
0
7
1
4
M
O
U
T
(
B
A
U
D
O
U
T
)
2
0
0
X
3
2
I
N
2
0
1
X
3
2
O
U
T
2
0
2
L
F
1
2
0
4
L
F
2
2
0
5
L
F
3
2
0
6
R
E
S
I
N
#
1
4
1
J
T
A
G
E
N
1
9
9
G
N
D
1
2
P
M
C
4
1
8
4
U1
ELAN
’8042CS#[XTDAT]’
VPP1
A20GATE
PGPD
PGPC
PGPB
1ICRST
8042CS#
RC#
MCE1#
MCE12#
REG1#
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
GND
VCCELA
p 15
p 16
p 17
p 18
p 19
p 20
p 21
p 22
p 23 |serpar.sch
|isabus.sch
|vlbus.sch
|power.sch
|upower.sch
|powersw.sch
|flopide.sch
|spares.sch
|spares1.sch
C11
0.01uF TANT
VCCEL3
VCCEL5
GND
GND
GND
C3
0.1UF
C4
0.1UF
GND
C189
10UF/10V
C1
0.01uF TANT
WP2
VPP2
BVD12
BVD11
WP1
2ICRST
ICDIR
CD1#
RDY1#
WAIT#
MCE2#
MCE22#
REG2#
CD2#
RDY2#
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’PULLUP’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’RSVD’
’PULLUP’
’PULLUP’
’PULLUP’
SA0
SA1
SA2
SA3
SA4
SA[0..12]
D[0..15]
’DRQ2[TDO]’
’AEN[TDI]’
’TC[TMS]’
SA[0..12]
DRQ2
IOCHRDY
TC
AEN
D[0..15]
IOR#
IOW#
EMEMR#
EMEMW#
OVCC3
1
2
JP1
HEADER 2
GND
ERESDRV
C230
33uF TANT
L4
1.2uH
RESIN#
XIORESET#
1
2
JP29
*HEADER 2
D0
D1
D2
D3
D4
D5
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
208-PQFP
ElanSC300/310
PE
BUSY
SLCT
BVD22
BVD21
ISA24
ISA25
ACK#
INIT#
ERR#
AFDT#
STRB#
SLCTIN#
PPDWE#
’[PPDSC#]’
’[X14OUT]’
’RSVD’
’RSVD’
’PULLUP’
’PULLUP’
VCCELSYS
VCCELMEM
GND
GND
GND
GND
C5
0.1UF
C6
0.1UF
C7
0.1UF
C8
0.1UF
GND
C190
10UF/10V
GND
C191
10UF/10V
MWE#
VCCELSY2
GND
C10
0.1UF
GND
C186
10UF/10V
SIN
SOUT
DTR#
RTS#
CTS#
DSR#
DCD#
RI#
PPOEN#
ROMCS#
DOSCS#
’RTS#/CFG0’
’DTR#/CFG1’
SCHEMATICS PROVIDED AS IS
AMD MAKES NO WARRANTY
EXPRESSED OR IMPLIED.
For Reference Only
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
’DBUFOE#’
’ENDIRH’
’ENDIRL’ SDEN#
SDRDH
SDRDL
SDEN#
SDRDH
SDRDL
Remove JP29 if using ElanSC300 rev B or
ElanSC310 without uPower mode.
Install JP29 if using ElanSC300 rev B or
ElanSC310 with uPower mode.
IOCS16#
MCS16#
IRQ14
BL1#
BL2#
BL3#
BL4#
R9
10K
SBHE#
R6
1K
R7
1K
R8
1K
VCC1
R2 33
R3 33
R4
33
R5 33
ELCS0L#
ELCS0H#
ELCS1L#
ELCS1H#
RAS0#
RAS1#
CAS0L#
CAS0H#
CAS1L#
CAS1H#
ELCS0H#
ELCS0L#
ELCS1H#
ELCS1L#
GND GND GND
VCCEL1
C201
10UF/10V
C202
0.1UF
C203
0.1UF
SA[13..23]
SA[13..23]
ElanSC300 Chip/schematic signal name
Note:
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
’
B
L
E
#
(
I
R
Q
1
1
)
’
’
B
H
E
#
(
I
R
Q
9
)
’
’
W
-
R
#
(
D
R
Q
7
)
’
’
M
-
I
O
#
(
D
R
Q
3
)
’
’
D
-
C
#
(
D
R
Q
0
)
’
’
A
D
S
#
(
O
W
S
#
)
’
’
R
S
V
D
(
P
U
L
L
U
P
)
’
’
P
U
L
L
U
P
(
I
R
Q
7
)
’
’
C
P
U
R
S
T
(
R
S
V
D
)
’
’
C
P
U
C
L
K
(
P
U
L
L
U
P
)
’
’
A
1
3
(
D
A
C
K
6
#
)
’
’
A
1
4
(
D
A
C
K
7
#
)
’
’
A
1
5
(
D
A
C
K
3
#
)
’
’
A
1
6
(
D
A
C
K
0
#
)
’
’
A
1
7
(
L
A
1
7
)
’
’
A
1
8
(
L
A
1
8
)
’
’
A
1
9
(
L
A
1
9
)
’
’
A
2
0
(
L
A
2
0
)
’
’
A
2
1
(
L
A
2
1
)
’
’
A
2
2
(
L
A
2
2
)
’
’
A
2
3
(
L
A
2
3
)
’
’
L
D
E
V
#
(
R
S
V
D
)
’
’
L
R
D
Y
#
(
D
R
Q
6
)
’
GND
’A12(BALE)’
’IRQ15’
’IRQ12’
’PULLDN(IRQ5)’
IOCHRDY
FRM1
CP11
LVEE#
LVDD#
CP21
DSMA[0..14]
DSMD[0..7]
LD0
LD1
LD2
LD3
M1
DSWE#
DSCE#
DSOE#
’PULLUP(IRQ10)’
’IRQ4’
’DRQ1’
’DACK5#’
’DRQ5’
’IOCHCHK#’
’DACK1#’
’CPURDY#(LMEG#)’
’PULLUP’
DSMD[0..7]
DSMA[0..14]
D
S
M
A
0
D
S
M
A
1
D
S
M
A
2
D
S
M
A
3
D
S
M
A
4
D
S
M
A
5
D
S
M
A
6
D
S
M
A
7
D
S
M
A
8
D
S
M
A
9
D
S
M
A
1
0
D
S
M
A
1
1
D
S
M
A
1
2
D
S
M
A
1
3
D
S
M
A
1
4
D
S
M
D
0
D
S
M
D
1
D
S
M
D
2
D
S
M
D
3
D
S
M
D
4
D
S
M
D
5
D
S
M
D
6
D
S
M
D
7
’ElanSC310 Chip signal name’