
ÉlanSC310 Microcontroller Evaluation Board User’s Manual
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1.
0
NOTE:
All I/O addresses are at AT-compatible locations.
Evaluation Board’s IRQ Mapping
Because the ÉlanSC310 microcontroller and the evaluation board are so
configurable, there is not one single IRQ map that covers all cases. What is
illustrated here is a typical memory map for the evaluation board configured in
Full ISA mode with the ÉlanSC310 microcontroller internal serial port enabled as
COM1, the Super I/O floppy drive controller enabled, an IDE hard drive, and the
Super I/O serial port enabled as COM2.
92h
ÉlanSC310 internal gate A20 and reset
control (internal to the ÉlanSC310)
Refer to the ÉlanSC310 Microcontrol-
ler Programmer’s Reference Manual.
80h–8Fh
DMA page registers.
Channels 0–7 (internal to the
ÉlanSC310).
70h–71h
RTC index and data registers (internal
to the ÉlanSC310).
NMI enable/disable (Bit 7 of Port 70).
MMSB is disabled which allows ac-
cesses to propagate to ISA bus.
60h, 64h
8042 keyboard control and data regis-
ter
See 8042 Spec.
61h
Port B control (internal to the
ÉlanSC310)
40h–43h
Programmable timer registers (internal
to the ÉlanSC310)
See 8254 Spec.
20h, 21h
Programmable IRQ master controller
(internal to ÉlanSC310)
See 8259 Spec.
0h–Fh
DMA controller channels 0–3 (inter-
nal to the ÉlanSC310)
See 8237A Spec.
I/O Address
Device Accessed
Special Notes
evalbd.book : ch4 Page 11 Thursday, August 8, 1996 2:34 PM