
ÉlanSC310 Microcontroller Evaluation Board User’s Manual
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Evaluation Board’s I/O Map
Because the ÉlanSC310 microcontroller and the evaluation board are so
configurable, there is not one single I/O map that covers all cases. What is illustrated
here is a typical memory map for the evaluation board configured in Full ISA mode
with the ÉlanSC310 microcontroller internal serial port enabled as COM1, the
Super I/O floppy drive controller enabled, an IDE hard drive, and the Super I/O
serial port enabled as COM2.
Table 4-3. Typical Full ISA I/O Map
I/O Address
Device Accessed
Special Notes
3F8h–3FFh
ÉlanSC310 internal 16C450 UART
3F0h–3F7h
IDE drive CS1,
Super I/O floppy drive controller
IDE CS1 selected using PGP2. Only
addresses 3F6 and 3F7 bit 7 are used
for IDE accesses.
3B0h–3DFh
Trident VGA card
3BCh–3BFh should be excluded from
this range. They are used for parallel
port accesses. Note this is a general ad-
dress range. Not all I/O locations in
this range are used.
3BCh–3BFh
ÉlanSC310 parallel port enabled as
LPT1:
Other I/O ranges for the ÉlanSC310
parallel port are 378h–37Fh and 278h–
27Fh.
398h–399h
Super I/O index and data ports
Used to enable Super I/O functions.
2F8h–2FFh
Super I/O serial port enabled as COM2
1F0h–1F7h
IDE drive CS0
IDE CS0 selected using PGP1.
10Ch–10Fh
Reserved
108h–10Bh
Reserved
100h–107h
PGP0 decode for V
PP
control
Set up using ÉlanSC310 Index 89h.
(Refer to “Programmable General Pur-
pose (PGP) Pins” on page 4-2.)
ECh–EFh
Reserved
E8h–EBh
Reserved
C0h–DEh
DMA controller channels 4–7 (internal
to the ÉlanSC310)
See 8237A Spec.
A0h, A1h
Programmable IRQ slave controller
(internal to the ÉlanSC310)
See 8259 Spec.
evalbd.book : ch4 Page 10 Thursday, August 8, 1996 2:34 PM