ÉlanSC310 Microcontroller Evaluation Board User’s Manual
C-2
1.
0
Phase-Locked Loops
Board layout considerations for the four PLLs suggest the following precautions:
• Keep the output traces for the four PLLs as short as possible and keep them as
far away from each other (and other clocking signals) as possible.
• Do not exceed the specified AC loading for the four PLL outputs. Certainly no
DC loading is allowed since they are all CMOS logic outputs. If the PLLs have
to drive more load than they are designed for in the actual application, make
sure they are properly buffered on the board.
Power Supplies
Board layout considerations for the power supplies suggest the following
precautions:
• Bring the analog V
CC
and digital V
CC
on separate traces from the output of the
voltage regulator to the ÉlanSC310 microcontroller; making sure the traces are
thick and wide. Filter the analog V
CC
with an RLC second-order low-pass filter
(e.g., R= 10
Ω
, L=47
µ
H, C=33
µ
F). Since the digital V
CC
carries much more
current than the analog V
CC
, a second order LC low-pass filter should be used
instead (i.e., the series resistor should be removed). A small capacitor in the
order of a few nanofarads can be added in parallel to the large filter capacitor
to suppress high-frequency noise.
• Isolate the analog ground plane from the digital ground plane on the board, and
connect them after decoupling.
evalbd.book : appc Page 2 Thursday, August 8, 1996 2:34 PM