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Command reference
R&S
®
ZND
1046
User Manual 1173.9557.02 ─ 61
The command affects only the transition filter registers, the
ENABle
registers, and
queue enabling:
●
The
ENABle
parts of the
STATus
:
OPERation
and
STATus
:
QUEStionable
... reg-
isters are set to all 1's.
●
The
PTRansition
parts are set all 1's, the
NTRansition
parts are set to all 0's,
so that only positive transitions in the
CONDition
part are recognized.
The status reporting system is also affected by other commands, see
"Reset values of the status reporting system"
Example:
STAT:PRES
Preset the status registers.
Usage:
Event
STATus:QUEStionable:CONDition?
STATus:QUEStionable:INTegrity:CONDition?
STATus:QUEStionable:INTegrity:HARDware:CONDition?
STATus:QUEStionable:LIMit<Lev>:CONDition?
Returns the contents of the
CONDition
part of the
QUEStionable...
registers.
Reading the
CONDition
registers is nondestructive.
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
Example:
STAT:QUES:LIMit:COND?
Query the
CONDition
part of the
QUEStionable:LIMit1
reg-
ister to retrieve the current status of the limit check.
Usage:
Query only
STATus:QUEStionable:ENABle
<BitPattern>
STATus:QUEStionable:INTegrity:ENABle
<BitPattern>
STATus:QUEStionable:INTegrity:HARDware:ENABle
<BitPattern>
STATus:QUEStionable:LIMit<Lev>:ENABle
<BitPattern>
Sets the enable mask which allows true conditions in the
EVENt
part of the
QUEStionable...
registers to be reported in the summary bit. If a bit is 1 in the
enable register and its associated event bit transitions to true, a positive transition will
occur in the summary bit (e.g. bit 10 of the
QUEStionable
register for the
LIMit1
register, bit 0 of the
LIMit1
register for the
LIMit2
register).
See also
Chapter 6.5.1, "Overview of status registers"
on page 609 and
"Reset values of the status reporting system"
Suffix:
<Lev>
.
Selects one of the two
QUEStionable:LIMit
registers; see
"STATus:QUEStionable:LIMit<1|2>"
SCPI command reference
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