38
Logic function blocks
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The input variable to INPUT is obtained delayed a settable time T at output OFF when
the input variable changes from 1 to 0 in accordance with the time pulse diagram, figure
12. The output OFF signal is set to 1 immediately when the input variable changes from
0 to 1.
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Содержание REO 517
Страница 10: ... RQWHQWV ...
Страница 16: ...6 Introduction to the application manual KDSWHU QWURGXFWLRQ ...
Страница 64: ...54 Blocking of signals during test KDSWHU RPPRQ IXQFWLRQV ...
Страница 88: ...78 Scheme communication logic ZCOM KDSWHU LQH LPSHGDQFH ...
Страница 100: ...90 Time delayed phase and residual overcurrent protection TOC1 KDSWHU XUUHQW Equation 36 Iset IsSEC I1b 100 ...
Страница 146: ...136 Unbalance protection for capacitor banks TOCC KDSWHU XUUHQW ...
Страница 166: ...156 Dead line detection DLD KDSWHU 3RZHU V VWHP VXSHUYLVLRQ ...
Страница 171: ...161 About this chapter KDSWHU RQWURO KDSWHU RQWURO ERXW WKLV FKDSWHU This chapter describes the control functions ...
Страница 293: ...283 About this chapter KDSWHU RJLF KDSWHU RJLF ERXW WKLV FKDSWHU This chapter describes the logic functions ...
Страница 378: ...368 Monitoring of DC analog measurements KDSWHU 0RQLWRULQJ ...
Страница 379: ...369 About this chapter KDSWHU 0HWHULQJ KDSWHU 0HWHULQJ ERXW WKLV FKDSWHU This chapter describes the metering functions ...
Страница 384: ...374 Pulse counter logic PC KDSWHU 0HWHULQJ ...
Страница 412: ...402 Serial communication modules SCM KDSWHU DWD FRPPXQLFDWLRQ ...
Страница 440: ...430 LED indication module KDSWHU DUGZDUH PRGXOHV ...