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Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 4:
Power-On and Power-Down Behavior Including Hibernate
Exiting Hibernate
The steps for exiting Hibernate are as follows.
1.
Reapply power to all rails that were switched off. Apply power in any sequence.
2.
Before FPGA initialization can begin, deassert PROGRAM_B to a High logic level. The
rising transition on PROGRAM_B must occur after turning all three power supplies
back on.
3.
After logic initialization, the FPGA releases the open-drain INIT_B signal. With
INIT_B High, the FPGA starts its configuration process.
4.
When configuration is complete, the FPGA enters the Start-up phase, asserts DONE,
and enables the I/Os, according to how the BitGen options are set.
5.
The FPGA is now ready for user operation.
Design Considerations
Be aware of how various pins are powered in the application. Most user-I/O pins,
including the dual-purpose configuration pins and the dedicated PROGRAM_B and
DONE pins, are powered by a specific V
CCO
supply input. Dedicated configuration pins
such as SUSPEND and the JTAG pins are powered by the V
CCAUX
supply. If disconnecting
power to any of these supplies, consider how that affects FPGA configuration when power
is re-applied.
For specific information on configuration pins and their associated power rails, refer to
UG380
,
Spartan-6 FPGA Configuration User Guide
.
