Spartan-6 FPGA Power Management
www.xilinx.com
11
UG394 (v1.1) September 4, 2012
Entering Suspend Mode
3.
After a delay of t
SUSPENDHIGH_AWAKE
, the FPGA drives the AWAKE output Low to
indicate that it is entering suspend mode.
4.
After a delay of t
SUSPEND_GTS
, the FPGA switches the normal behavior of all outputs
over to the suspend mode behavior defined by the SUSPEND attribute assigned to
each I/O. See
Define the I/O Behavior During Suspend Mode, page 15
.
5.
After a delay of t
SUSPEND_DISABLE
, FPGA inputs are blocked and the interconnect shut
off (High) to prevent any internal switching activity.
Exiting Suspend in
Figure 1-2
6.
The system drives the FPGA's SUSPEND input Low, causing the FPGA to exit suspend
mode. If using multi-pin wake-up mode, the system first drives the FPGA's SUSPEND
input LOW, then drives any of the enabled multi-pin wake-up pins High, causing the
FPGA to exit suspend mode.
7.
The FPGA releases the inputs and interconnect after a delay of t
SUSPEND_ENABLE
,
allowing signals to propagate internally. There is no danger of corrupting the internal
state because all clocked primitives are still write protected.
8.
After a delay of t
SUSPENDLOW_AWAKE
or t
SCP_AWAKE
, the FPGA asserts the AWAKE
signal with the bitstream
option
drive_awake:yes
. If the option is
drive_awake:no
,
then the FPGA releases AWAKE to become an open-drain output. In this case, an
external pull-up resistor is required or an external signal must drive AWAKE High
before the FPGA continues to awaken. All subsequent timing is measured from when
the AWAKE output transitions High. If multiple FPGAs are waking up and need to be
synchronized, set
drive_awake:no
in each and then use an external pull-up resistor to
synchronize the AWAKE pins. If other devices are waking up and the FPGA(s) need to
wait, set
drive_awake:no
and use an external signal to control the AWAKE pin and
drive it High once the rest of the system is ready.
9.
After a delay of t
AWAKE_GTS
, the FPGA switches output behavior from the specified
SUSPEND attribute to the function specified in the FPGA application. The timing of
this switch-over is controlled by the suspend/wake
sw_gts_cycle
bitstream
generation setting, which defines when the FPGA's internal global three-state (GTS)
control is released. After the specified number of clock cycles, the outputs are active
according to the normal FPGA application. By default, the outputs are enabled four
clock cycles after AWAKE goes High. The outputs are generally released before the
clocked primitives to allow signals to propagate out of the FPGA.
10. After a delay of t
AWAKE_GWE
, the writable, clocked primitives are released according
to the suspend/wake
sw_gwe_cycle
bitstream generator setting, which defines when
the FPGA's internal global write enable (GWE) control is asserted. After the specified
cycle, it is again possible to write to flip-flops, block RAM, distributed RAM (LUT
RAM), shift registers (SRL), and I/O latches. By default, the clocked primitives are
released five clock cycles after AWAKE transitions High. The write-protect lock should
be held until after outputs are enabled.
