Spartan-6 FPGA Power Management
www.xilinx.com
9
UG394 (v1.1) September 4, 2012
Entering Suspend Mode
The FPGA can only enter suspend mode if enabled in the configuration bitstream (see
Enable the Suspend Feature and Glitch Filtering, page 14
). The SUSPEND pin must be Low
during power up and configuration. Once enabled through the bitstream, and the
SUSPEND_SYNC primitive is not present in the design, when the SUSPEND pin is
asserted, the FPGA unconditionally and quickly enters suspend mode.
If the SUSPEND_SYNC primitive is present in the design, the FPGA does not enter
suspend mode until the suspend-acknowledge signal (SACK) is asserted. After the
SUSPEND pin is asserted, the SREQ port of the SUSPEND_SYNC primitive transitions
High. This can be used in the design to initiate any functions that must be completed prior
to the FPGA entering suspend mode. When these functions are complete, drive the SACK
port High.
After the FPGA enters suspend mode, all nonessential FPGA functions are shut down to
minimize power dissipation. The FPGA retains all configuration data while in suspend
mode. After entering suspend mode, all writable clocked primitives are write-protected
against spurious write operations, and all FPGA inputs and interconnects are shut down.
This allows the design state to be held static during suspend mode. If a specific design state
must be maintained, see
Design Requirements to Maintain Application Data, page 17
.
X-Ref Target - Figure 1-1
Figure 1-1:
Entering Suspend Mode
S
U
S
PEND
Attri
bu
te
S
U
S
PEND
Attri
bu
te
Glitch Filter
Sus
pend En
ab
le
S
RL
LUT RAM
Flip-Flop
s
L
a
tche
s
Block RAM
Writ
ab
le Clocked Primitive
s
FPGA Applic
a
tion Logic
FPGA
Inp
u
t
s
FPGA
O
u
tp
u
t
s
S
U
S
PEND
AWAKE
ENABLE_
S
U
S
PEND
ENABLE_
S
U
S
PEND
Filter
S
elect
Write-Protect Writ
ab
le
Clocked Primitive
s
Apply
S
U
S
PEND Attri
bu
te
to FPGA O
u
tp
u
t
s
Block FPGA
Inp
u
t
s
S
U
S
PEND_
S
YNC
S
U
S
PEND_
S
YNC
In
s
t
a
nti
a
ted
UG
3
94_c1_01_020
3
10
S
REQ
S
ACK
