Spartan-6 FPGA Power Management
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27
UG394 (v1.1) September 4, 2012
VCCO
Setting the V
CCAUX
Level
The user must set the CONFIG V
CCAUX
attribute according to the voltage being provided
to the V
CCAUX
rails. The valid values for this attribute are 2.5 (default) or 3.3. This attribute
affects the banking rules for I/O placement within the automated placer, as well as in the
pin assignments tool. It also affects the end-generated bitstream for the device. The
V
CCAUX
attribute is a global attribute for the Spartan-6 device and is not attached to any
particular primitive.
CONFIG VCCAUX=3.3;
V
CCAUX
Specifications
Both the 2.5V and 3.3V settings for V
CCAUX
allow a variation (2.375V to 2.625V, or 3.15V to
3.45V). The data retention voltage is the same for both at 2.0V, so more care must be taken
with a 2.5V rail to not let it drop more than 0.5V. See
DS162
,
Spartan-6 FPGA Data Sheet: DC
and Switching Characteristics
for complete specifications.
The CONFIG V
CCAUX
attribute is used by the ISE® Design Suite software to determine if
LVCMOS25 inputs can be powered by V
CCAUX
. If CONFIG V
CCAUX
= 2.5, V
CCAUX
is used
to power LVCMOS25 inputs. If CONFIG V
CCAUX
= 3.3, V
CCO
must be 2.5V for any banks
with LVCMOS25 inputs. Setting V
CCAUX
to match whichever is more common between
LVCMOS25 and LVCMOS33 can help optimize placement.
There are some slight changes to resistor values depending on whether V
CCAUX
is set to
2.5V or 3.3V. The I/O pull-down resistor values are lower for a V
CCAUX
of 3.3V. The
differential termination resistor (DIFF_TERM) can be more tightly controlled around 100
Ω
when V
CCAUX
is 3.3V. See
DS162
,
Spartan-6 FPGA Data Sheet: DC and Switching
Characteristics
and the Spartan-6 FPGA IBIS models at:
http://www.xilinx.com/support/download/index.htm
V
CCO
V
CCO
powers the I/O resources, and has separate rails for each bank of I/O for maximum
flexibility. All of the V
CCO
connections to a specific I/O bank must be connected to the
same voltage. The V
CCO
voltage can be 1.2V to 3.3V, depending on the output standard
specified for a given bank. Most devices have four I/O banks, while the XC6SLX75/T and
larger in the FG(G)676 and FG(G)900 packages offer six I/O banks. The V
CCO
pins for a
bank should all be tied to a supply rail, even if the bank is completely unused.
In a 3.3V-only application, all V
CCO
supplies and V
CCAUX
connect to 3.3V. Spartan-6
FPGAs allow bridging between different I/O voltages and standards by applying different
voltages to the V
CCO
inputs of different banks. Refer to the I/O banking rules section in
UG381
,
Spartan-6 FPGA SelectIO Resources User Guide
for the I/O standards that can be
mixed within a single I/O bank.
The Spartan-6 FPGA V
CCO
ranges support variation around the nominal supply voltage.
Refer to
DS162
,
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
for specific
voltage levels.
