Spartan-6 FPGA Power Management
www.xilinx.com
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UG394 (v1.1) September 4, 2012
ISE Design Suite Power Optimization
Saving Clock Routing Power
Clocks are a significant aspect of power consumption because of their high fanout nets and
also because controlling them limits the number of logic primitives toggling in a design. If
possible, stop the clock where it enters the FPGA, so that it does not consume any FPGA
power. If the clock can not be gated externally, then disable it inside the FPGA using the
BUFGCE primitive. Avoid using logic to gate clocks, since CLB logic introduces
route-dependent skew and makes the design sensitive to the timing hazards of lot-to-lot
variations. Minimizing the amount of routing a clock net uses is helpful, since the Xilinx
software automatically disables clock nets where possible for unused areas of CLBs.
If possible, minimize the number of DCMs or PLLs required in the design. A single PLL
can be shared with both halves of a GTP_DUAL transceiver. A DCM_CLKGEN can be
used to dynamically scale clock frequency as needed for the application, helping to
minimize power.
ISE Design Suite Power Optimization
Power can also be reduced automatically in the Xilinx design tools. With goal-based
implementation, the ISE Design Suite offers a simple, one-step process to specify power
optimization. Design Goals and Strategies control the implementation tools by using
preset process properties designed to achieve a particular design goal. Power optimization
attempts to meet timing constraints as well as reduce power consumption.
For guidelines on design techniques to reduce power consumption, see the Power
Advantage page at:
http://www.xilinx.com/products/technology/power/index.htm
