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Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 5:
Power Estimation
If necessary, slow the supply voltage ramp to control the charge current. If foldback is not
a design requirement, it is best to avoid it, keeping the power-supply design simple.
Various power-supply manufacturers offer complete power solutions for Xilinx FPGAs
including some with integrated three-rail regulators specifically designed for Xilinx
FPGAs.
Saving Power
Lower-power consumption not only reduces power supply requirements but also reduces
heat, which increases reliability, allows for smaller form factor packaging, and helps
eliminate heat sinks and fans. Spartan-6 FPGAs are designed to minimize power
consumption without sacrificing high performance and low cost.
The lowest power state is the quiescent state with no inputs toggling, all outputs disabled,
and no pull-up or pull-down resistors in use. This static power state is often dominated by
transistor leakage current, which can increase at smaller process geometries. Xilinx has
made major advances in the design of the 45 nm Spartan-6 devices. Comparing Spartan-6
FPGAs to Spartan-3A FPGAs, the average static power in Spartan-6 devices is lower.
Quiescent current levels are specified in
DS162
,
Spartan-6 FPGA Data Sheet: DC and
Switching Characteristics
. The lower-power Spartan-6 LX devices offer the lowest quiescent
current.
Dynamic (active) power is a function of capacitance, voltage, and frequency (CV
2
f). In
general, capacitance decreases as transistors shrink. But smaller transistors allow users to
take advantage of more of them per device, while using faster switching rates, which can
lead to increases in dynamic power. Dynamic power consumption can be reduced by
reducing the number or frequency of nodes and I/O toggling in a design. Consider the
following techniques to eliminate any unnecessary switching in a design and reduce
dynamic power:
•
Bring all incoming signals to a static state
•
Apply rail-to-rail levels to inputs wherever possible
•
Turn off as many outputs as possible
•
Assign signal standards with small swings to outputs
•
Use lower output drive and slower slew rates
•
Tie all unused inputs to V
CCO
or GND outside the device
•
Avoid instantiating pull-up and pull-down resistors on I/Os
•
Reduce the total length of heavy loaded signals to reduce capacitance
•
Disable as many internal oscillating circuits as possible
•
Have block RAMs operate in NOCHANGE
mode to reduce toggling of the outputs of
the block RAM
