Spartan-6 FPGA Power Management
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29
UG394 (v1.1) September 4, 2012
Chapter 3
Lower-Power Spartan-6 LX Devices
Introduction
The lower-power Spartan-6 LX devices (-1L) meet lower quiescent and dynamic current
levels than the standard Spartan-6 LX devices. They also operate at a reduced V
CCINT
of
1.0V, versus the 1.2V of the standard Spartan-6 family, thus reducing core power. The
lower-power Spartan-6 LX devices are supported by the -1L speed grade. Although the -1L
devices are slower than the standard Spartan-6 LX family's slowest speed grade (-2), an
additional 30–40% power savings is attained.
Use L1 as the speed grade when ordering the lower-power Spartan-6 LX devices, which is
also the way the speed grade is marked on the device. For example, the FPGA ordered as
the XC6SLX16-L1CSG324 is marked as either L1C for commercial temperature range or L1I
for industrial temperature range.
Designing Using the Lower-Power Spartan-6 LX Devices
To design for the lower-power Spartan-6 LX devices, select the appropriate device during
implementation. A design targeted to the lower-power Spartan-6 LX devices can be
defined using all the same methods and options as available to the standard Spartan-6 LX
devices. All primitives that support the Spartan-6 LX family also support the lower-power
Spartan-6 LX devices. The lower-power Spartan-6 LX devices can be selected using the ISE
Design Suite in the Project Navigator. Different from the ordering code or actual device
marking, the Xilinx tools display the part number with an appended L (for example,
XC6SLX16L). The only speed grade supported for these devices is the -1L. The same speed
grade supports both the commercial and industrial temperature ranges.
The resulting bitstream is identical in format between the standard Spartan-6 LX devices
and the lower-power Spartan-6 LX devices. The JTAG device IDCODEs are identical and
the iMPACT software identifies the device under the same standard Spartan-6 FPGA part
number. However, there are small implementation differences between the two families,
including a reset circuit used for the DCM CLKFX output (see the
RST Input Logic
section
of
UG382
,
Spartan-6 FPGA Clocking Resources User Guide
), and differences in block RAM
configuration. Therefore, the designer must target the correct device both to generate the
correct timing information, and to account for implementation differences between the
two families. The standard and lower-power Spartan-6 LX device bitstreams can not be
used in both families. A standard Spartan-6 LX device should not be powered at 1.0V, and
a lower-power Spartan-6 LX device should not be powered at 1.2V.
