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Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 4:
Power-On and Power-Down Behavior Including Hibernate
The V
CCO_2
supplies are part of the POR circuit, because the primary configuration pins
are in bank 2. V
CCO_2
is typically at 2.5V or 3.3V for the configuration interface. Make sure
V
CCO_2
reaches the proper level for POR and for configuration, especially if it is reduced
after configuration for a lower-voltage I/O standard such as LVCMOS15 or LVCMOS12.
For information on the power-on reset step as part of the configuration process, see
Device
Power-Up
in
UG380
,
Spartan-6 FPGA Configuration User Guide
.
Supply Sequencing
The Spartan-6 FPGA can be powered up and powered down in any sequence. Because the
three FPGA supply inputs must be valid to release the POR and can be supplied in any
order, there is no FPGA-specific voltage sequencing requirement. Although the FPGA has
no specific voltage sequence requirements, any potential sequencing requirement of the
configuration device attached to the FPGA, such as an SPI serial Flash PROM, a parallel
NOR Flash PROM, or a microcontroller should be considered. For example, Flash PROMs
have a minimum time requirement before the PROM can be selected, and this time must be
considered if the 3.3V supply is the last in the sequence. See
Power-On Sequence Precautions
in
UG380
,
Spartan-6 FPGA Configuration User Guide
.
Ramp Rate
The power supplies should ramp monotonically within the power supply ramp time range
specified in
DS162
,
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
. To ensure
successful power-on, V
CCINT
, V
CCO
bank 2, and V
CCAUX
supplies must rise through their
respective threshold-voltage ranges with no dips. The maximum ramp time for V
CCINT
in
the lower-power Spartan-6 LX devices is slightly lower than for the standard family
because of the reduced voltage.
Hot Swap
Hot swap, also known as hot plug or hot insertion, refers to plugging an unpowered board
into a powered system. To support hot swap, an unpowered board or device must be able
to be plugged directly into a powered system or backplane without affecting or damaging
the system or the board/device. Spartan-6 FPGAs are fully hot swap compliant and
include the following I/O features:
•
Signals can be applied to I/O pins before powering the device
•
I/O pins are high-impedance (that is, three-stated) before and throughout the
power-up and configuration processes
•
There is no current path from the I/O pin back to the voltage supplies
Power rails can be disabled in any order without damage to the FPGA. It is recommended
that all I/O pins be ignored after any of the power rails (V
CCINT
, V
CCO
, or V
CCAUX
) drops
below its minimum operating voltage. To transition cleanly from valid signals to the
disabled state, either first disable the outputs in the design, or shut down V
CCO
followed
by V
CCAUX
and then V
CCINT
.
