Spartan-6 FPGA Power Management
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UG394 (v1.1) September 4, 2012
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Revision History
The following table shows the revision history for this document.
Date
Version
Revision
05/18/10
1.0
Initial Xilinx release.
09/04/12
1.1
• Updated
Additional Documentation
section.
• In
Chapter 1
, deleted first and last paragraphs from
Differential I/O Standards
.
Eliminated statements pertaining to differential drivers and receivers disabled in
suspend mode. Reinforced the directive that the SUSPEND pin must be tied to GND
when the suspend feature is disabled by adding “or High” to second paragraph of
SUSPEND Pin
. Changed “X” to “0” in first row of
Table 1-5
. Changed the AWAKE
output pin power supply to V
CCO
power rail on bank 1 in third paragraph of
AWAKE
Pin Behavior when Suspend Feature is Enabled
. Added “for Recommended
Operating Conditions” to data sheet power levels referenced in
FPGA Voltage
Requirements During Suspend Mode
.
• In
Chapter 2
, changed “used” to “being programmed” in description section, last row,
of
Table 2-1
. Added V
CCAUX
setting restriction paragraphs to
VCCAUX
. Removed
“
±5%” specification from first paragraph in
VCCAUX Specifications
and third
paragraph of
VCCO
.
• In
Chapter 3
, removed “approximately one speed grade slower (~15%)” from first
paragraph in
Introduction
. Added a UG382 reference to
Designing Using the
Lower-Power Spartan-6 LX Devices
. Added V
CCAUX
and IODELAY2 specification
paragraphs to
Lower-Power Spartan-6 LX Device Specifications
.
• In
Chapter 5
, removed “50%” specification from second paragraph in
Saving Power
.
Also remove last sentence referencing techniques for past FPGA families from last
paragraph in
ISE Design Suite Power Optimization
.
