Xilinx Spartan-6 FPGA Series, User Manual

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10 www.xilinx.com Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1: Power Management With Suspend Mode
Each FPGA output pin or bidirectional I/O pin assumes its defined suspend mode
behavior, which is described as part of the FPGA design using a SUSPEND attribute.
The AWAKE pin goes Low, indicating that the FPGA is in suspend mode. The DONE pin
remains High while the FPGA is in suspend mode because the FPGA configuration data is
not lost.
This section details the waveform notes in Figure 1-2 .
Entering Suspend in Figure 1-2
1. An external signal drives the FPGA's SUSPEND pin High, unconditionally forcing the
FPGA into the power-saving suspend mode (if SUSPEND_SYNC is not used). When
SUSPEND_SYNC is used, this phase does not complete until the SACK port of the
SUSPEND_SYNC primitive is asserted. Data values are captured for I/O pins with a
SUSPEND attribute set to DRIVE_LAST_VALUE; however, this value is not presented
until Step 4.
2. In response to the SUSPEND input going High or SACK assertion on the
SUSPEND_SYNC primitive, and after a delay of t
SUSPEND_GWE
, the FPGA write
protects and preserves the states of all clocked primitives. The states of all flip-flops,
block RAM, distributed RAM (LUT RAM), shift registers (SRL), and I/O latches are
preserved during suspend mode.
X-Ref Target - Figure 1-2
Figure 1-2: Suspend Mode Waveforms (Entering and Exiting)
u g 3 94_c1_02_042910
Blocked
t
S U S PEND_DI S ABLE
t
AWAKE_GWE
t
AWAKE_GT S
S U S PEND Inp u t
AWAKE O u tp u t
Flip-Flop s , Block RAM,
Di s tri bu ted RAM
FPGA O u tp u t s
FPGA Inp u t s ,
Interconnect
Write Protected
Defined b y S U S PEND Attri bu te
1
2
3
4
5
6
7
8
10
9
Entering Sus pend Mode Exiting Sus pend Mode
sw_gts_cycle
sw_gwe_cycle
t
S U S PEND_ENABLE
t
S U S PENDLOW_AWAKE
t
S U S PEND_GT S
t
S U S PENDHIGH_AWAKE
t
S U S PEND_GWE