Spartan-6 FPGA Power Management
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17
UG394 (v1.1) September 4, 2012
Suspend Mode Wake-Up Timing Controls
Design Requirements to Maintain Application Data
When a design requires that application data be preserved when entering suspend mode,
the SUSPEND_SYNC primitive should be used. When the FPGA enters suspend mode, the
global write enable (GWE) is removed, maintaining the state of all flip-flops and user
RAM. The FPGA requires a delay of t
SUSPEND_GWE
between recognizing a High on the
SUSPEND pin and disabling GWE internally. This is the first event after SUSPEND
transitions High, before AWAKE toggles, and before the inputs are disabled if
SUSPEND_SYNC is not used. During this delay, additional user clocks to flip-flops or
RAM can continue to update their contents. Since the GWE signal can have some skew
between locations on the device, some locations can be disabled while others remain
enabled on the last clock edge before GWE takes full effect. This situation can be avoided
when using the SUSPEND_SYNC feature. After the suspend request is driven out of the
SUSPEND_SYNC primitive, disable the clocks and/or clock enables on the logic that must
retain its current state. After the disable is complete, drive the SACK port of the
SUSPEND_SYNC primitive and the FPGA begins the process to enter suspend mode.
To avoid initializing the flip-flops when exiting suspend mode, choose
en_sw_gsr:No
.
Exiting suspend mode should be synchronized to a user clock to avoid race conditions
corrupting the application data. Inputs are enabled first, allowing control signals to
continue to hold off the toggling of storage primitives. The assertion of GWE can be
synchronized to a user clock to align it with a system clock edge.
Suspend Mode Wake-Up Timing Controls
When exiting suspend mode, the wake-up sequence for the FPGA is programmable and
controlled by a single clock.
Wake-Up Timing Clock Source
The wake-up timing when exiting suspend mode is controlled by a selectable clock source
as shown in
Figure 1-4
and described in
Table 1-3
. The clock source is defined by one or
two bitstream generator options,
sw_clk
and sometimes
StartupClk
.
The internal oscillator is disabled during suspend mode to conserve power.
