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Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 4:
Power-On and Power-Down Behavior Including Hibernate
Forcing FPGA to Quiescent Current Levels
Before removing the power supplies, it is recommended to first put the device into the
quiescent state. Pulse PROGRAM_B Low to achieve the quiescent current levels. Driving
PROGRAM_B Low forces all I/Os into a high-impedance state, ceases all internal
switching, and converts the bitstream held in internal memory to all zeros. During and
after the Low pulse on PROGRAM_B, disable the internal pull-up resistors on all I/Os by
driving the HSWAPEN input High. Holding PROGRAM_B Low continues clearing the
configuration memory. To minimize quiescent current, release PROGRAM_B High but
hold off configuration by holding INIT_B Low, or by setting the Mode pins to a slave or
JTAG configuration mode and disabling the external configuration clock (CCLK or TCK).
To restart the application, release PROGRAM_B High and in slave or JTAG modes, enable
the external configuration source. The FPGA must reconfigure before the application
restarts. No state information is preserved. If the application must retain the FPGA
configuration bitstream, then use the suspend mode.
Entering Hibernate State
Hibernate starts with the approach described in
Forcing FPGA to Quiescent Current
Levels, page 34
. Hibernate provides further power savings by switching off power rails.
This state reduces quiescent power consumption to the lowest possible level. The FPGA
enters Hibernate by switching off the V
CCINT
(core), V
CCAUX
(auxiliary), and V
CCO
(output) power supplies. Power FETs with low on resistance are recommended to perform
the switching action. Configuration data is lost upon entering Hibernate; therefore, the
device reconfigures after exiting the state.
Holding the PROGRAM_B input Low during the transition into Hibernate keeps all FPGA
output drivers in a high-impedance state. Release PROGRAM_B after re-applying power.
See
Design Considerations, page 36
for recommended levels on Dedicated and
Dual-Purpose pins.
X-Ref Target - Figure 4-2
Figure 4-2:
Spartan-6 FPGA Power-Off Diagram
V
CCAUX
PROGRAM_B
Active Device
Connected on
Bo
a
rd
UG
3
94_c4_02_111109
Power
S
witch
2.5V/
3
.
3
V
1.2V/1.0V
V
CCINT
V
CCO
V
CCO
Su
pply
S
p
a
rt
a
n-6
FPGA
