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Spartan-6 FPGA Power Management
UG394 (v1.1) September 4, 2012
Chapter 1:
Power Management With Suspend Mode
The AWAKE output pin is supplied by the V
CCO
power rail on bank 1.
When the option
drive_awake:yes
is set, the AWAKE pin is an active output driver,
equivalent to a user I/O configured as LVCMOS, with a 12 mA output drive and a fast
slew rate.
Controlling Wake-Up from an External Source
The default option is
drive_awake:no
. The
drive_awake:no
option signifies that the
AWAKE pin is an open-drain output capable of sinking 12 mA. In this case, an external
pull-up resistor is required to exit suspend mode. To minimize the amount of current flow
during suspend mode, the resistor value should be high. The resistor needs to be strong
enough to overcome the I/O pin leakage. A large resistor value also equates to a longer
AWAKE rise time. The FPGA does not exit suspend mode and begin the wake-up process
until AWAKE transitions High.
Synchronizing Wake-Up
The wake-up process can be synchronized across multiple FPGAs or between the FPGAs
and the system by using one SUSPEND signal to control multiple devices. The AWAKE pin
can also synchronize multiple devices. To start the wake-up process at the same time, the
AWAKE pins of multiple FPGAs can be tied to a single pull-up resistor. The wake-up
counters can also be synchronized if
sw_clk:StartupClk
and
StartupClk:UserClk
.
Holding the AWAKE pin Low delays the transition from suspend mode to active mode by
holding off the
sw_gwe_cycle
and
sw_gts_cycle
counters, and allows an external
controller to decide when to begin the wake-up process in the FPGA.
Post-Configuration CRC Limitations When Using Suspend Mode
To minimize power, post-configuration CRC checking stops during suspend mode.
If an active application uses the post-configuration CRC feature and an error occurs, do not
enter suspend mode. If there is a CRC error, the FPGA does not wake from suspend mode
without reprogramming, such as asserting PROGRAM_B or power-cycling the FPGA.
X-Ref Target - Figure 1-5
Figure 1-5:
AWAKE Output Drive Options if Suspend Mode Enabled
AWAKE
AWAKE
Intern
a
l
Aw
a
ke
S
ign
a
l
Intern
a
l
Aw
a
ke
S
ign
a
l
LVCMO
S
12 mA
FA
S
T
LVCMO
S
12 mA
FA
S
T
O
O
T
(OE)
FPGA
FPGA
V
CC
20 k
Ω
drive_
a
w
a
ke=yes
drive_
a
w
a
ke=no
Extern
a
l P
u
ll-
u
p
Re
s
i
s
tor Re
qu
ired
UG
3
94_c1_05_121009
