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HDMI 1.4/2.0 TX Subsystem

PG235 October 4, 2017

www.xilinx.com

Appendix

Verification, Compliance, and Interoperability

For Video PHY Controller settings and PLL selections, see the

Video PHY Controller

LogiCORE IP Product Guide

(PG230)

[Ref 24]

Similarly,

Figure A-2

shows the hardware setup for Native Video Interface. The only

difference is that two Video Bridge modules are added in between the HDMI RX Subsystem

and the Test Pattern Generator, and between the Test Pattern Generator to the HDMI TX

Subsystem.

This is because the Test Pattern Generator can be configured to generate certain video

pattern in AXI4-Stream video format, which can be used to test the HDMI TX Subsystem

alone instead of relying on the video received from the HDMI RX Subsystem.

X-Ref Target - Figure A-1

Figure

‐

Test Setup for AXI4-Stream Video Interface

HDMI RX

Subsystem

HDMI TX

Subsystem

Video PHY Controller

MicroBlaze/

Zynq-7000 SoC/

Zynq US+

UART

I2C

Test

Pattern

Generator

AXI4-Stream
Video

AXI-Lite

HDMI Source

HDMI Sink

X16567-033016

Send Feedback

Summary of Contents for HDMI 1.4

Page 1: ...HDMI 1 4 2 0 Transmitter Subsystem v3 0 LogiCORE IP Product Guide Vivado Design Suite PG235 October 4 2017...

Page 2: ...escriptions 19 Clocks and Resets 35 Chapter 3 Designing with the Subsystem General Design Guidelines 36 Interlaced Video 42 Clocking 45 Resets 48 Chapter 4 Design Flow Steps Customizing and Generating...

Page 3: ...bug Tools 83 Hardware Debug 84 Interface Debug 85 Appendix C Application Software Development Device Drivers 88 Appendix D Additional Resources and Legal Notices Xilinx Resources 105 Documentation Nav...

Page 4: ...over AXIS compliant YUV420 Support Optional HPD Active polarity IP Facts LogiCORE IP Facts Table Subsystem Specifics Supported Device Family 1 UltraScale Families GTHE4 UltraScale Architecture GTHE3...

Page 5: ...e in the Vivado Integrated Design Environment IDE for performance and quality Applications High Definition Multimedia Interface HDMI is a common interface used to transport video and audio and is seen...

Page 6: ...HDMI Stream after timeout This timeout is based on system CPU clock For example if system is running at 100 Mhz the IP times out after approximately 4 hours of normal operation when Hardware Evaluatio...

Page 7: ...on top of an HDMI TX core Various supporting modules are added around the HDMI TX core with respect to your configuration The HDMI TX core is designed to support native video interface however many of...

Page 8: ...ve Video Interface The HDMI TX Subsystem also provides an option to support a native video interface When Native Video Interface is selected the HDMI TX Subsystem is constructed without the Video Timi...

Page 9: ...TX Subsystem device driver has an abstract layer of API to allow you to implement certain functions This AXI4 Lite slave interface supports single beat read and write data transfers no burst transfers...

Page 10: ...2 0 spec Bit 1 TMDS_BIt_Clock_Ratio Bit 0 Scrambling_Enable Automatically handled by HDMI TX subsystem driver at Stream Start through the API XV_HdmiTxSs_StreamStart Two underlining subcore API driver...

Page 11: ...ding the information frame API function call You also need to calculate your own CRC and place the CRC at the right location so that the HDMI Sink is able to decode the InfoFrame This is an example of...

Page 12: ...value PB0 the ECC values are ignored Refer to section 5 2 3 4 and 5 2 3 5 of the HDMI 1 4 Specification Ref 12 for more information on the InfoFrame structure AUX Packets Handling This section descri...

Page 13: ...packet including calculating CRC in its application software and call XV_HdmiTxSs_SendGenericAuxInfoframe API The recommended place to push the packet is in HDMI TX Vsync interrupt callback void XV_H...

Page 14: ...tion The supported fields are highlighted in yellow with respective to the packet type General Control Packet Pixel Packing Phase and Color depth information are retrieved from video stream and sent t...

Page 15: ...www xilinx com Chapter 2 Product Specification AVI Infoframe Color space and VIC information are retrieved from video stream and sent through AVI Infoframe Other fields are not updated and remain as...

Page 16: ...ontent Protection HDCP transmitters are designed for transmission of audiovisual content securely between two devices that are HDCP capable In this HDMI TX Subsystem both HDCP 1 4 and HDCP 2 2 Transmi...

Page 17: ...of the HDCP protocols are active at any given time and the other is passive by calling the relevant HDMI TX Subsystem API functions For more details on HDCP see the HDCP v1 4 Product Guide PG224 Ref 2...

Page 18: ...x UltraScale FPGAs Data Sheet DC and AC Switching Characteristics DS892 Ref 2 Virtex UltraScale FPGAs Data Sheet DC and AC Switching Characteristics DS893 Ref 3 Kintex 7 FPGAs Data Sheet DC and AC Swi...

Page 19: ...m has three default interfaces AXI4 Lite control interface S_AXI_CPU_IN Video Interface VIDEO_OUT Audio Interface AUDIO_OUT X Ref Target Figure 2 11 Figure 2 11 HDMI TX Subsystem Pinout AXI4 Stream Vi...

Page 20: ...B 1 6 B67 786B 1 VBD LBFSXBDFON VBD LBFSXBDUHVHWQ VBD LVBDXGLRBDFON VBD LVBDXGLRBDUHVHWQ VBD LVBYLGHRBDFON VBD LVBYLGHRBDUHVHWQ DFUBFWV DFUBQ DFUBYDOLG YLGHRBFON ILG KSG 1 B 7 B287 1 B 7 B287 1 B 7 B2...

Page 21: ...erface HDCP 2 2 Only 6B B 38B 1 8 2B 1 9 2B 1 6 B67 786B 1 VBD LBFSXBDFON VBD LBFSXBDUHVHWQ VBD LVBDXGLRBDFON VBD LVBDXGLRBDUHVHWQ VBD LVBYLGHRBDFON VBD LVBYLGHRBDUHVHWQ DFUBFWV DFUBQ DFUBYDOLG YLGHRB...

Page 22: ...4 HDMI TX Subsystem Pinout AXI4 Stream Video Interface HDCP 1 4 and HDCP 2 2 6B B 38B 1 8 2B 1 9 2B 1 6 B67 786B 1 VBD LBFSXBDFON VBD LBFSXBDUHVHWQ VBD LVBDXGLRBDFON VBD LVBDXGLRBDUHVHWQ VBD LVBYLGHRB...

Page 23: ...ive Video Interface No HDCP S_AXI_CPU_IN AUDIO_IN VIDEO_IN SB_STATUS_IN s_axi_cpu_aclk s_axi_cpu_aresetn s_axis_audio_aclk s_axis_audio_aresetn acr_cts 19 0 acr_n 19 0 acr_valid video_clk hpd LINK_DAT...

Page 24: ...6B B 38B 1 8 2B 1 9 2B 1 6 B67 786B 1 VBD LBFSXBDFON VBD LBFSXBDUHVHWQ VBD LVBDXGLRBDFON VBD LVBDXGLRBDUHVHWQ DFUBFWV DFUBQ DFUBYDOLG YLGHRBFON KSG 1 B 7 B287 1 B 7 B287 1 B 7 B287 OLQNBFON B287 LUT Y...

Page 25: ...2 2 Only S_AXI_CPU_IN AUDIO_IN VIDEO_IN SB_STATUS_IN s_axi_cpu_aclk s_axi_cpu_aresetn s_axis_audio_aclk s_axis_audio_aresetn acr_cts 19 0 acr_n 19 0 acr_valid video_clk hpd LINK_DATA1_OUT LINK_DATA2_...

Page 26: ...DDC_OUT irq video_rst VIDEO_IN_tdata 3 BPC PPC 1 0 VIDEO_IN_active_video VIDEO_IN_vsync VIDEO_IN_hsync hdcp22_irq hdcp22_timer_irq S_AXI_CPU_IN AUDIO_IN VIDEO_IN SB_STATUS_IN s_axi_cpu_aclk s_axi_cpu_...

Page 27: ...ite address S_AXI_CPU_IN_awprot Input 3 Write address protection S_AXI_CPU_IN_awvalid Input 1 Write address valid S_AXI_CPU_IN_awready Output 1 Write address ready S_AXI_CPU_IN_wdata Input 32 Write da...

Page 28: ...ve Video Input Interface Table 2 3 shows the signals for Native video input interface This interface is a standard video interface and runs at video_clk clock rate The data width is user configurable...

Page 29: ...ts 2 video_clk is generated by Video PHY Controller LogiCORE IP Product Guide PG230 Ref 24 3 When native video interface is selected there is no hardware reset 4 You must provide the correct video tim...

Page 30: ...abled in the system ensure that the audio data is properly sent to their perspective channel allocation Unused channels must be packed with zero i e Mute to avoid audio channel swapping which means au...

Page 31: ...a 0 LINK_DATA0_OUT_tvalid Output 1 Link Data 0 Valid LINK_DATA1_OUT_tdata Output 40 Link data 1 LINK_DATA1_OUT_tvalid Output 1 Link Data 1 Valid LINK_DATA2_OUT_tdata Output 40 Link data 2 LINK_DATA2_O...

Page 32: ...to securely store and retrieve the keys to be loaded into the HDCP 2 2 drivers For the detailed list of keys that are required to be loaded by the user application see the HDCP v2 2 Product Guide PG2...

Page 33: ...Stream Video Interface Name Direction Width Description hpd Input 1 If XGUI option Hot Plug Detect Active High Default 0 Hot Plug Detect is released 1 Hot Plug Detect is asserted If XGUI option Hot P...

Page 34: ...gnal then the HPD polarity must be set to Active Low in HDMI Transmitter Subsystem GUI Table 2 11 Miscellaneous Signals with Native Video Interface Name Direction Width Description hpd Input 1 If XGUI...

Page 35: ...rs s_axis_video_aclk Input 1 AXI4 Stream video input clock s_axis_video_aresetn Input 1 Reset associated with s_axis_video_aclk active Low Resets the AXI4 Stream data path for the video input s_axis_a...

Page 36: ...ycle is illustrated in Figure 3 1 The data is captured when both the valid TVLD and ready TRDY signals are asserted The HDMI 1 4 2 0 Transmitter Subsystem expects the channels in sequential order If t...

Page 37: ...at where InstancePtr is a pointer to XV_HdmiTxSs instance format is a selector of Audio Format 1 HBR 0 L PCM Note The L PCM Packet Type 0x02 allows you to pack up to 24 bits of audio from the Audio Da...

Page 38: ...ormat Max Bits Per Component 16 ELWV ELWV 9 ELWV ELWV ELWV 5 9 ELWV 5 9 ELWV 5 9 ELWV 5 9 ELWV 8 ELWV 8 ELWV 8 ELWV 8 ELWV ELWV ELWV ELWV ELWV ELWV 5 9 ELWV 5 9 ELWV ELWV 5 9 ELWV 5 9 ELWV 8 ELWV 8 EL...

Page 39: ...ully compliant with the AXI4 Stream video protocol A data format for a fully compliant AXI4 Stream video protocol with dual pixels per clock is illustrated in Figure 3 5 Table 3 1 Max Bits Per Compone...

Page 40: ...12 24 36 48 60 84 96 108 72 120 144 132 Y0 12 bits U0 12 bits Y1 12 bits V0 12 bits Y2 12 bits U2 12 bits Y3 12 bits V2 12 bits RGB YUV444 8 bits RGB YUV444 10 bits YUV422 12 bits G0 Y0 12 bits B0 U0...

Page 41: ...example Figure 3 8 illustrates the YUV 4 2 0 AXI4 Stream video data representation in AXI4 Stream Video IP and System Design Guide Ref 14 However in the native HDMI video interface the video data repr...

Page 42: ...d pixels per clock design In this case it is more difficult for the system to meeting timing requirements Therefore the quad pixels per clock data mapping is recommended for design intended to send hi...

Page 43: ...traightforward for progressive video Taking 1920x1080 50Hz I as an example the detail timing information is shown in Table 3 2 For interlaced video each frame consists two fields One field carries the...

Page 44: ...0 has 522 lines and Field 1 has 523 lines Interlaced Video with Pixel Repetition For some video formats with TMDS rates below 25 Mhz e g 13 5 for 480i NTSC can be transmitted using pixel repetition sc...

Page 45: ...clk s_axis_audio_aclk link_clk and video_clk respectively The audio streaming clock must be greater than or equal to 128 times the audio sample frequency Because audio clock regeneration is not part o...

Page 46: ...clock 594 MHz Link clock 594 MHz 4 148 5 MHz Pixel clock This is the internal pixel clock This clock is not used in the system It is only listed to illustrate the clock relations for 8 bpc pixel clock...

Page 47: ...ted in HDMI TX Subsystem and the relationship to the Video PHY Controller The HDMI TX Subsystem is able to support either AXI4 Stream Video or Native Video Video Resolution Horizontal Total Horizontal...

Page 48: ...o data and other auxiliary data into Link Data and sent to Video PHY Controller at Link Clock Based on the system requirement Video PHY Controller is generating Link Clock and Video Clock for HDMI TX...

Page 49: ...ansmitter Subsystem can be added to a Vivado IP integrator block design in the Vivado Design Suite and can be customized using IP catalog For more detailed information on customizing and generating th...

Page 50: ...arted UG910 Ref 17 Note Figures in this chapter are illustrations of the Vivado Integrated Design Environment IDE The layout depicted here might vary from the current version Top Level Tab The Top lev...

Page 51: ...for example 720p60 has a total horizontal pixel of 1650 which is not divisible by 4 are not supported If the design is intended to support this kind of video formats ensure that PPC 2 is selected in...

Page 52: ...vel of the frame buffer that is the number of locations that are considered the minimum fill level for FIFO operation to start Generally this value should be between 12 and 20 It must be at least 16 l...

Page 53: ...owable options are Pass Through and Tx Only where Pass Through showcases the HDMI system built with one HDMI TX Subsystem and one HDMI RX Subsystem sharing the same Video PHY Controller Tx Only showca...

Page 54: ...e Design Overview Section A system block digram to show the overview of the example design to be generated Native Video Interface Option The native video interface option window is shown in Figure 4 4...

Page 55: ...ryption C_INCLUDE_HDCP_1_4 Exclude Exclude Untick FALSE Include Tick TRUE Include HDCP 2 2 Encryption C_INCLUDE_HDCP_2_2 Exclude Exclude Untick FALSE Include Tick TRUE Video over AXIS compliant NTSC P...

Page 56: ...ple Design Design Topology C_EXDES_TOPOLOGY 0 Pass Through 0 Tx Only 1 TX PLL Type C_EXDES_TX_PLL_SELECTION 0 GTXE2 6 GTHE3 4 CPLL 0 QPLL GTXE2 QPLL01 GTHE3 4 3 6 RX PLL Type C_EXDES_RX_PLL_SELECTION...

Page 57: ...eo PHY Controller modules link_clk and video_clk are generated from the Video PHY Controller Therefore the clock constraints are set to the Video PHY Controller constraints instead of these generated...

Page 58: ...s section is not applicable for this IP subsystem Transceiver Placement This section is not applicable for this IP subsystem I O Standard and Placement This section is not applicable for this IP subsy...

Page 59: ...xilinx com Chapter 4 Design Flow Steps Simulation Simulation of the subsystem is not supported Synthesis and Implementation For details about synthesis and implementation see the Vivado Design Suite U...

Page 60: ...ter Subsystem by using Vivado Flow Summary HDMI 1 4 2 0 Transmitter Subsystem allows users to customize the example design based on their system requirements It offers the full flexibility with the fo...

Page 61: ...of the HDMI solution HDCP is used to securely send audiovisual data from an HDCP protected transmitter to HDCP protected downstream receivers Typically HDCP 2 2 is used to encrypt content at Ultra Hig...

Page 62: ...uitry X Ref Target Figure 5 1 Figure 5 1 KC705 KCU105 ZC706 HDMI Example Design Block Diagram X Ref Target Figure 5 2 Figure 5 2 ZCU102 HDMI Example Design Block Diagram KC705 KCU105 ZC706 Evaluation...

Page 63: ...x_video_clk tx_tmds_clk HDMI TX Subsystem rxoutclk rx_video_clk Cable Driver DP159 tx_tmds_clk_p n tx_tmds_data 2 0 HDMI TX HDMI RX rx_tmds_clk_p n axis_tx_tmds_data_ch 2 0 rx_tmds_clk HDMI RX Subsyst...

Page 64: ...MI_TX_SS for HDMI stream conversion then to the VPHY for transmission High level control of the system is provided by a simplified embedded processor subsystem containing I O peripherals and processor...

Page 65: ...Generator Only for MicroBlaze based processor subsystem Clocking Wizard Processor System Reset AXI UARTLite Only for MicroBlaze based processor subsystem AXI Interrupt Controller Only for MicroBlaze b...

Page 66: ...roject 2 In the pop up window press Next until you get to the page to select Xilinx part or board for the project 3 Select the Board KC705 KCU105 ZC706 and ZCU102 are supported 4 Click Finish 5 Click...

Page 67: ...October 4 2017 www xilinx com Chapter 5 Example Design You can rename the IP component name which is used as example design project name 6 Configure HDMI 1 4 2 0 Transmitter Subsystem then click OK X...

Page 68: ...te the example design 8 Right click on the HDMI 1 4 2 0 Transmitter Subsystem component under Design source and click Open IP Example Design 9 Choose the target project location then click OK The IPI...

Page 69: ...n Local to Project for the example design 12 Launch SDK File Launch SDK 13 Choose SDK workspace location By default it is Local to Project Vivado SDK is launched 14 Create Board Support Package in Viv...

Page 70: ...your own HDCP encryption keys into the EEPROM FMC or on board To hdcp_key_utility application X Ref Target Figure 5 11 Table 5 1 Applications for Example Design Board Processor Topology Import Example...

Page 71: ...e design to decrypt the HDCP keys The application is terminated after completing the programming of HDCP keys Note The keys only need to be programmed into the EEPROM once Formatting HDCP Keys for HDC...

Page 72: ...s are the header 4 license constant 36 bytes and key set 862 so the total is 902 bytes Note If a pass through example design is built which contains HDMI RX component you can use the same hdcp_key_uti...

Page 73: ...apply power to the VADJ power rail for the HDMI 2 0 FMC card TB FMCH HDMI4K Most new boards are per programmed and should be detected The VADJ is powered when the DS19 LED located near the power swit...

Page 74: ...Settings 5 In the next menu select a Set FMC VADJ to 1 8V b IMPORTANT Ensure that the jumpers are set correctly on their HDMI 2 0 FMC daughter card Migration Notes When migrating from version 2016 3...

Page 75: ...d to the Example Design Application software You do not need to choose HDCP 1 4 or HDCP 2 2 from UART A corresponding HDCP is selected according to the capability of connected source sink If the devic...

Page 76: ...0 Transmitter Subsystem has been validated using Kintex 7 FPGA Evaluation Kit KC705 Kintex UltraScale FPGA Evaluation Kit KCU105 Inrevium Artix 7 FPGA ACDC A7 Evaluation Board Zynq 7000 All Programma...

Page 77: ...tem translates the LINK DATA into AXI4 Stream Video and sends to the Test Pattern Generator By setting the Test Pattern Generator to pass through mode the AXI4 Stream Video from the HDMI RX Subsystem...

Page 78: ...the Test Pattern Generator and between the Test Pattern Generator to the HDMI TX Subsystem This is because the Test Pattern Generator can be configured to generate certain video pattern in AXI4 Strea...

Page 79: ...e supported in the design with PPC set to 4 X Ref Target Figure A 2 Figure A 2 Test Setup for Native Video Interface HDMI RX Subsystem HDMI TX Subsystem Video PHY Controller MicroBlaze Zynq 7000 SoC Z...

Page 80: ...60 2160 1600 1250 1200 60 wuxgap60 2592 1920 1245 1200 60 wsxgap60 2240 1680 1089 1050 60 Notes 1 Not all resolutions can be supported due to VPHY limitation For details refer to Video PHY Controller...

Page 81: ...60 800 640 525 480 60 svgap60 1056 800 628 600 60 wxgap60 1440 1280 790 768 60 wxga p60 1792 1366 798 768 60 uxgap60 2160 1600 1250 1200 60 wuxgap60 2592 1920 1245 1200 60 wsxgap60 2240 1680 1089 1050...

Page 82: ...ith the HDMI 1 4 2 0 Transmitter Subsystem This guide along with documentation related to all products that aid in the design process can be found on the Xilinx Support web page or by using the Xilinx...

Page 83: ...f the design labeled DO NOT MODIFY To contact Xilinx Technical Support navigate to the Xilinx Support web page Debug Tools Tools are available to address HDMI 1 4 2 0 Transmitter Subsystem design issu...

Page 84: ...hardware debug The signal names mentioned in the following individual sections can be probed using the debug feature for debugging the specific problems General Checks Ensure that all the timing cons...

Page 85: ...and State Information At system start up While changing video stream from UART Menu VPHY log GT init start GT init done TX frequency event TX timer event TX MMCM reconfig done QPLL reconfig done GT TX...

Page 86: ...subsystem configuration AXI4 Stream Audio Interface To ensure that the audio is working in HDMI 1 4 2 0 Transmitter Subsystem the AXI4 Stream must be constructed as described below The HDMI 1 4 2 0 Tr...

Page 87: ...h6 are X The preambles for audio ch1 ch3 ch5 ch7 are always Y through out of the whole audio block An illustration of 8 channel audio is shown below If 8 channel audio is enabled in your design only 6...

Page 88: ...rs to configure the sub core IP blocks Architecture The subsystem driver provides an easy to use well defined API to help integrate the subsystem in an application without having to understand the und...

Page 89: ...ilinx Video PHY Controller which itself is independent and offer flexible architecture with multiple protocol support Both MAC and PHY are dynamically programmable through the AXI4 Lite interface X Re...

Page 90: ...ecause the application knows what video format will be sent and what audio format will be embedded With this information the ACR number can be calculated and set before audio stream is ready to be sen...

Page 91: ...set TX DDC u Disable VPHY TMDS output buffer when HPD is asserted u Enable VPHY TMDS output buffer when HPD is released HDMI TX TX Stream Up Intr N Y u Configure HDMI Retimer chip if needed u Enable T...

Page 92: ...miTxSs HdmiTxSs 3 In the subsystem driver instance there is a metadata structure to store the subsystem hardware configuration Declare a pointer variable in the application code to point to the instan...

Page 93: ...owing HDCP configurations HDCP 1 4 only HDCP 2 2 only and both When both protocols are enabled the common HDCP driver ensures that only one is active at any given time HDCP TX Driver Integration This...

Page 94: ...ction is given adequate CPU runtime especially during authentication attempts XV_HdmiTxSs_HdcpPoll 6 Optionally set the HDCP protocol capability The default option is both which means that if both HDC...

Page 95: ...heck the status of the cipher encryption This is the instantaneous encryption status of the cipher and can change between subsequent frames For repeater or pass through applications special care must...

Page 96: ...phy h that defines the subsystem object 2 Declare and allocate space for a Video PHY Controller instance in your application code Example XVphy Vphy 3 In the Video PHY Controller instance there is a m...

Page 97: ...m initialization is completed Registering the Video PHY Controller interrupts are part of system application integration Steps are shown in the previous section and not repeated here Interrupts All in...

Page 98: ...ndlers are defined in xv_hdmitxss h XV_HDMITXSS_HANDLER_CONNECT XV_HDMITXSS_HANDLER_VS XV_HDMITXSS_HANDLER_STREAM_UP XV_HDMITXSS_HANDLER_STREAM_DOWN XV_HDMITXSS_HANDLER_HDCP_AUTHENTICATE Table C 1 Map...

Page 99: ...dmi20 XV_HdmiTxSs InstancePtr 4 Now the HDMI sink has been detected retrieve the sink EDID information and store it in a local buffer 256 bytes using the following API int XV_HdmiTxSs_ReadEdid XV_Hdmi...

Page 100: ...8 Enable XV_HDMITXSS_HANDLER_HDCP_AUTHENTICATE This interrupt is triggered when a cable is connected a HDCP 1 4 or HDCP 2 2 is enabled and HDCP is entering an authentication state The callback functio...

Page 101: ...eate an example design which contains all the procedures implemented and can serve as a reference for integrating the HDMI 1 4 2 0 Transmitter Subsystem into your system Example Use Cases In this sect...

Page 102: ...rmat XVidC_ColorDepth Bpc XVidC_3DInfo Info3D Example TmdsClock XV_HdmiTxSs_SetStream HdmiTxSsPtr VideoMode ColorFormat Bpc NULL 3 Set the Video PHY Controller TX reference clock VphyPtr HdmiTxRefClkH...

Page 103: ...ePtr u8 AudioChannels Example XV_HdmiTxSs_SetAudioChannels HdmiTxSs N 3 To demo using example design application software update the following section of codes in xhdmi_example c Enable 2 channel audi...

Page 104: ...nstancePtr void AuxPtr You must set the data byte value before calculating the CRC Example Channel Allocation InstancePtr HdmiTxPtr Aux Data Byte 4 0x13 You may choose to construct your own infoframe...

Page 105: ...cumentation Navigator DocNav From the Vivado IDE select Help Documentation and Tutorials On Windows select Start All Programs Xilinx Design Tools DocNav At the Linux command prompt enter docnav Xilinx...

Page 106: ...C and AC Switching Characteristics DS923 11 Zynq UltraScale MPSoC Data Sheet DC and AC Switching Characteristics DS925 12 HDMI specifications www hdmi org manufacturer specification aspx 13 HDCP speci...

Page 107: ...mation if not all audio channels are used Added Information about Native Video Added Information about Interlaced Video 04 05 2017 2 0 Removed single pixel per clock support 11 30 2016 2 0 Added examp...

Page 108: ...ials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of Sale which can be viewed at https www xilinx...

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