HDMI 1.4/2.0 TX Subsystem
65
PG235 October 4, 2017
Chapter
5:
Example Design
Example Design Specifics
In addition to the Video PHY Controller, HDMI Transmitter Subsystem and HDMI Receiver
Subsystem core, the complete example design includes the following cores:
• MicroBlaze or Zynq or Zynq Ult
• MicroBlaze Debug Module (Only for MicroBlaze based processor subsystem)
• AXI Interconnect
• Local Memory Bus (Only for MicroBlaze based processor subsystem)
• LMB BRAM Controller (Only for MicroBlaze based processor subsystem)
• Block Memory Generator (Only for MicroBlaze based processor subsystem)
• Clocking Wizard
• Processor System Reset
• AXI UARTLite (Only for MicroBlaze based processor subsystem)
• AXI Interrupt Controller (Only for MicroBlaze based processor subsystem)
• AXI IIC
• AXI GPIO
• Video Test Pattern Generator
• AXI4-Stream Register Slice
• Utility Buffer
• Utility Vector Logic
X-Ref Target - Figure 5-6
Figure
5
‐
6:
HDMI Reference Design Block Diagram (Zynq or Zynq Ult)
tpg_ss
audio_ss
zynq_ss/zynq_us_ss
ZYNQ or
ZYNQ Ult
Clock Wizard
Processor
System Reset
Module
AXI interconnect (AXI lite)
Audio Pattern
Gen
AXI IIC
FPGA IO
Clock Wizard
HDMI ACR
AXI GPIO
Test Pattern
Generator
HDMI
Transmitter
Subsystem
HDMI
Receiver
Subsystem
Video PHY
Controller
DDR
UART
