HDMI 1.4/2.0 TX Subsystem
35
PG235 October 4, 2017
Chapter
2:
Product Specification
Clocks and Resets
provides an overview of the clocks and resets. See
for more information.
Table
2
‐
12:
Clocks and Resets
Name
Direction
Width
Description
s_axi_cpu_aclk
Input
1
AXI4-Lite CPU control interface clock.
s_axi_cpu_aresetn
Input 1
Reset, associated with s_axi_cpu_aclk
(active-Low). The s_axi_cpu_aresetn signal
resets the entire subsystem including the data
path and AXI4-Lite registers.
s_axis_video_aclk
Input
1
AXI4-Stream video input clock.
s_axis_video_aresetn
Input 1
Reset, associated with s_axis_video_aclk
(active-Low). Resets the AXI4-Stream data path
for the video input.
s_axis_audio_aclk
Input 1
AXI4-Stream Audio input clock. (The audio
streaming clock must be greater than or equal
to 128 times the audio sample frequency)
s_axis_audio_aresetn
Input 1
Reset, associated with s_axis_audio_aclk
(active-Low). Resets the AXI4-Stream data path
for the audio input.
link_clk
Input 1
HDMI Link data output clock. This connects to
the Video PHY Controller Link clock output.
video_clk
Input
1
Clock for the native video interface.
Notes:
1. The reset should be asserted until the associated clock becomes stable.
