Xilinx HDMI 1.4, Product Manual

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HDMI 1.4/2.0 TX Subsystem 79
PG235 October 4, 2017 www.xilinx.com
Appendix A: Verification, Compliance, and Interoperability
Table A-1 , Table A-2 , and Table A-3 show the video resolutions that were tested as part of
the release for different video formats. The following limitations apply:
• When Number of pixels per clock on AXI4-S output (PPC) set to 4, only video
formats with total horizontal resolution divisible by 4 are supported. For example, a
video resolution 720p60 has horizontal total pixel 1650, which is not divisible by 4.
Therefore, it can't be supported in the design with PPC set to 4.
X-Ref Target - Figure A-2
Figure A ‐ 2: Test Setup for Native Video Interface
HDMI RX
Subsystem
HDMI TX
Subsystem
Video PHY Controller
MicroBlaze/
Zynq-7000 SoC/
Zynq US+
UART
I2C
Test
Pattern
Generator
AXI4-Stream
Video
AXI-Lite
Video to
AXI4-
Stream
Bridge
AXI4-
Stream
to
Video
Bridge
Native Video
HDMI Source HDMI Sink
X16568-033016
Table A ‐ 1: Tested Video Resolutions for RGB 4:4:4 and YCbCr 4:4:4
Resolution
Horizontal Vertical
Frame
Rate (Hz)
Total Active Total Active
480i60 858 720 525 480 60
576i50 864 720 625 576 50
1080i50 2640 1920 1125 1080 50
1080i60 2200 1920 1125 1080 60
480p60 858 720 525 480 60
576p50 864 720 625 576 50
720p50 1980 1280 750 720 50
720p60 1650 1280 750 720 60
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