Transmeta Crusoe TM5500, System Design Manual

Page: 5 / 130

July 17, 2002
5
List of Tables
Table 1: Supported ACPI Processor States ...................................................................... 11
Table 2: Supported ACPI System States........................................................................... 11
Table 3: Power Net Naming Conventions.......................................................................... 12
Table 4: Signal Naming Conventions ................................................................................ 12
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors .................. 22
Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes................................23
Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM ............................... 24
Table 8: MAX1718 Core Power Supply Output Control Selector ......................................25
Table 9: MAX1718 DSX Voltage Configuration ................................................................. 26
Table 10: Power Supply Sequencing Timing Specifications................................................ 35
Table 11: DDR SDRAM Memory Configurations ................................................................. 51
Table 12: SDR SDRAM Memory Configurations ................................................................. 65
Table 13: SDR SDRAM Interface Device Specifications ..................................................... 68
Table 14: Write Timing Compensation ................................................................................ 69
Table 15: Signal Pull-up/Pull-down Requirements .............................................................. 87
Table 16: PLD Pinout........................................................................................................... 94
Table 17: Recommended Eight Layer PCB Stackup ......................................................... 113
Table 18: Standard Spacing/Line/Via Constraints ............................................................ 113
Table 19: Extended Global Spacing/Line/Via Constraints ................................................ 114
Table 20: Extended Physical Constraints ......................................................................... 115
Table 21: Extended Electrical Constraints ........................................................................ 115