July 17, 2002
47
Processor Power Supplies and Power
Management
This type of system is expected to have a typical C2 en exit latency of 8.5 µS, and a worst-case C2
en exit latency of 15 µS.
Example 2 (C3)
A system designer may implement a system with the following C3 characteristics:
•
The power management controller waits 64 µS after receiving the Stop Grant cycle before it asserts the
processor SLEEP# signal.
•
The power management controller waits 32 µS between asserting the processor SLEEP# signal and
asserting the clock generator CPU_STP# signal.
•
In response to a wake event from C3, the power management controller de-asserts the clock generator
CPU_STP# signal no earlier than 2 µS after it asserted the clock generator CPU_STP# signal.
•
The clock generator requires < 12 µS for restarting the processor CPU_CLK# upon deassertion of the
clock generator CPU_STP# signal.
•
The power management controller waits 32 µS between de-asserting the clock generator CPU_STP#
signal and de-asserting the processor SLEEP# signal.
•
The power management controller waits 64 µS between de-asserting the processor SLEEP# signal and
de-asserting the processor STPCLK# signal.
This type of system is expected to have a worst-case C3 en exit latency of 207 µS.
Example 3 (C3)
A system designer may implement a system with the following C3 characteristics:
•
The power management controller waits 2 µS after receiving the Stop Grant cycle before it asserts the
processor SLEEP# signal.
•
The power management controller waits 32 µS between asserting the processor SLEEP# signal and
asserting the clock generator CPU_STP# signal.
•
In response to a wake event from C3, the power management controller de-asserts the clock generator
CPU_STP# signal no earlier than 2 µS after it asserted the clock generator CPU_STP# signal.
•
The clock generator requires < 12 µS for restarting the processor HCLK# upon deassertion of the clock
generator CPU_STP# signal.
•
The power management controller waits 32 µS between de-asserting the clock generator CPU_STP#
signal and de-asserting the processor SLEEP# signal.
•
The power management controller waits 60 nS between de-asserting the processor SLEEP# signal and
de-asserting the processor STPCLK# signal.
This type of system is expected to have a worst-case C3 en exit latency of 82 µS.
Summary of Contents for Crusoe TM5500
Page 1: ...TM5500 TM5800 System Design Guide July 17 2002...
Page 6: ...July 17 2002 6 List of Tables...
Page 8: ...July 17 2002 8 List of Figures...
Page 50: ...July 17 2002 50 Processor Power Supplies and Power Management...
Page 110: ...July 17 2002 110 System Design Considerations...
Page 122: ...July 17 2002 122 System Design Checklists...
Page 128: ...July 17 2002 128 Serial Write protection PLD Data...
Page 130: ...July 17 2002 130 Index...
