Transmeta Crusoe TM5500, System Design Manual

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July 17, 2002
9
C h a p t e r 1
Introduction and Naming
Conventions
1.1 Overview
This design guide is organized into the following sections:
• Introduction and Naming Conventions (this chapter) introduces the conventions used in this document,
including possible differences between hardware names for power supplies, pins, etc. and the reference
schematics used throughout the document.
• Chapter 2, Example System Block Diagram and Schematics presents the Crusoe TM5500/TM5800
processor in the context of a block diagram that shows necessary components and their connections.
The reference schematic for the processor itself is also provided.
• Chapter 3, Processor Power Supplies and Power Management describes the power supply network in
detail.
• Chapter 4, DDR Memory Design provides design guidelines and layout requirements for incorporating
DDR SDRAM memory into a design.
• Chapter 5, SDR Memory Design provides design guidelines and layout requirements for incorporating
SDR SDRAM memory into a design.
• Chapter 6, System Design Considerations describes a variety of design issues, including clocking, reset,
ROM interfaces, signal pull-up/pull-down requirements, thermal sensor, and southbridge interfaces.
• Chapter 7, PCB Layout Guidelines discusses physical issues related to memory and component
interfaces, power supplies, signal integrity, mounting and spacing constraints, tolerances and fabrication
guidelines, and footprint and pin escape diagrams.
• Appendix A, System Design Checklists includes cross-referenced checklists to follow while designing a
system.
• Appendix B, Serial Write-protection PLD Data includes the JEDEC fuse map and CUPL source code for
the write-protection PLD required for serial-ROM Code Morphing software placement. This issue is
described in
Serial Flash ROM Write Protection Circuit on page 93 in Chapter 6, System Design
Considerations .
• An Index is also included.