Transmeta Crusoe TM5500, System Design Manual

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July 17, 2002
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C h a p t e r 6
System Design Considerations
6.1 Clocking
The TM5500/TM5800 processor primary clock input (CLK_CPU0) requires a 60 or 66 MHz clock signal. This
clock input is compatible with Pentium™ class clock generators. The processor generates the internal
processor core clock and the SDRAM clocks for both memory interfaces from the primary clock input.
The processor also expects a PCI clock (CLK_PCI_TM) input of CLK_CPU/2. The phase relationship
between the processor and PCI clocks should be such that the CLK_CPU leads CLK_PCI_TM by 3.3 nS
(typical). The clock traces (including CLK_CPU and CLK_PCI_TM) from the clock generator to each PCI
connector or device should be of equal lengths.
The schematics on the following pages illustrate two possible clock generation circuits. One uses an
Integrated Circuit Systems ICS9248-192 clock generator. The other uses an International Microcircuits
IMIXG571CYB clock generator. The ICS clock generator solution has a much smaller overall footprint.
Note
For detailed TM5500/TM5800 processor clock specifications see the Input Clocks section in the Data Book.