Transmeta Crusoe TM5500, System Design Manual

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July 17, 2002
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Example System Block Diagram and
Schematics
TM5500/TM5800 processors include both core processor and northbridge functionality. For a motherboard
designer, this means the processor looks very much like a northbridge. TM5500/TM5800 processors support
two DRAM interfaces, one for Double Data Rate (DDR) SDRAMs and the other for Single Data Rate (SDR)
SDRAMs. Designers can choose to use either or both SDRAM interfaces, depending on their system cost
and performance requirements.
In the block diagram, note that power signals that feed each component are listed in the component’s block.
This helps to identify suspend and switched power distribution to each component. Descriptions of each
supply are described in Chapter 3,
Processor Power Supplies and Power Management .
The major elements shown in the block diagram are outlined below:
• Processor Core Power Supply . The processor core high-efficiency switched-mode power supply. See
Chapter 3, Processor Power Supplies and Power Management .
• Memory Power Supplies . The power supplies for SDR and DDR SDRAM memory. See Chapter 3,
Processor Power Supplies and Power Management .
• DDR SDRAM Interface . The processor can support up to two identical banks of DDR SDRAMs in
various configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 4, DDR
Memory Design .
• SDR SDRAM Interface . The processor can support up to four banks of SDR SDRAMs in various
configurations of 64-Mbit, 128-Mbit, 256-Mbit, and 512-Mbit devices. See Chapter 5, SDR Memory
Design .
• SDRAM High-speed Bidirectional Level-translator Isolation . Signal isolation is used to ensure that
CKE signals to the SDRAMs remain stable during processor power transitions. Since the processor does
not have a suspend power well, output signals are undefined during power transitions and subject to
glitching.
• PCI Interface and PCC Signals . The PCI interface is 33 MHz, 3.3 V. The arbiter supports five REQ/GNT
pairs. CLKRUN is supported (see Using CLKRUN on page 98). PCC (PC compatibility) signals are used
for communication with the southbridge. See Southbridge on page 98.
• Code Morphing Software Serial Flash ROM . Code Morphing software is stored in this optional (but
recommended) 1 Mbyte device. See Serial Flash ROM Interface on page 91. Other options for Code
Morphing software code storage (such as sharing the BIOS ROM) are also described. See Combined
BIOS/CMS Parallel ROM Interface on page 96.
• Serial Flash Write-protection Circuit . If a serial flash ROM is used for Code Morphing software, a PLD
(programmable logic device) write-protection device must be added to the serial flash ROM circuit. See
Serial Flash ROM Write Protection Circuit on page 93.
• Mode-bit ROM (required) . System-dependent configuration options vital to proper processor operation
are stored in this required 2 Kbit device and read by the processor at boot time. See Mode-bit ROM on
page 89.
• Thermal Sensor . An external thermal sensor is used in conjunction with a thermal sensing diode built
into the processor. See Thermal Diode and Thermal Sensor on page 103.
• Transmeta Debug Module (TDM) Interface . This adds some low-level debug support to facilitate in-
design bring-up, as well as connectivity to the Transmeta Virtual In-Circuit Emulator CE (TMVICE) for
software development. See
TDM Debug Interface Connection on page 107.