Transmeta Crusoe TM5500, System Design Manual

Page: 53 / 130

July 17, 2002
53
DDR Memory Design
4.4 DDR Reference Voltage
The VDDIO25 power supply pins of the processor are connected to V2_5. The DDR interface has a
DDR_VREF pin whose input should be derived from that power supply using a 1% resistor voltage divider.
The specification for this input is described in the
Data Book . Two examples are provided below for selecting
DDR_VREF divider resistor values.
• For a DDR_VREF specification of 1.25 V, the recommended V2_5 voltage divider network for deriving
DDR_VREF is: upper resistor (tied to V2_5) = 2490
Ω
, and lower resistor (tied to ground) = 2490
Ω
.
• For a DDR_VREF specification of 1.35 V, the recommended V2_5 voltage divider network for deriving
DDR_VREF is: upper resistor (tied to V2_5) = 1960
Ω
, and lower resistor (tied to ground) = 2320
Ω
.
4.4.1 DDR Reference Voltage Noise Filter Circuit
TM5500/TM5800 processors require a ferrite bead noise filter on the C_VREF DDR interface reference
voltage signal. C_VREF is derived from IOVDD25 (2.5 V I/O power supply) using a resistive voltage divider.
The recommended noise filter circuit is shown below.
Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter
R2
2.32K
1%
GND
V2_5
C1
0.1uF
R1
1.96K
1%
C_VREF_A
GND
C_VREF
FB2
100 Ohms @ 100 MHz
0805
C_VREF
K19
U1A
Crusoe BGA474
NOTE:
PLACE FB2 AS CLOSE AS
POSSIBLE TO PROCESSOR
BALL K19
TM5500/TM5800
Processor