Transmeta Crusoe TM5500, System Design Manual

Page: 117 / 130

July 17, 2002
117
A p p e n d i x A
System Design Checklists
The checklist Status field is for designers and implementers to use as the project progresses. Use as follows:
Status Description
P Task is pending (waiting for other assistance, etc.)
C Coding - implementation/testing in progress
V Implementation verified
O Other group’s function
blank Task not begun
Power Supply Checklist
Item Description Status
1. Processor power supply ramp-up must be properly sequenced. See Chapter 3, Power
Supply Sequencing in the System Design Guide for details on power sequencing
requirements.
2. The VRDA (VID) pin connections between the processor and the V_CPU_CORE (CVDD)
regulator should meet the following requirements:
•
The processor VRDA outputs are open-drain, and therefore require pull-ups. If the
VRM controller does not have internal pull-ups on its VID inputs, then external pull-up
resistors must be used. At no time can the VRDA signals be pulled up to a voltage
greater than 3.3 V plus a diode drop.
• Ensure that VRDA signals are connected to the correct corresponding VID pins
(VRDA[0] to VID[0], etc.)
3. The POWERGOOD output of the V_CPU_CORE (CVDD) regulator must not glitch during
LongRun power management transitions. Designs that do glitch must include a low pass
filter, isolated from down-stream logic, to remove the glitch from the regulator
POWERGOOD output. Note that regulators qualified by Transmeta for TM5500/TM5800
processor have their POWERGOOD output blanked during transitions to alleviate this
problem.