Transmeta Crusoe TM5500, System Design Manual

Page: 121 / 130

July 17, 2002
121
System Design Checklists
Other Signals Checklist
Item Description Status
1. Correct pull-up and pull-down resistors should be configured as described in Chapter 6,
Signal Pull-ups and Pull-downs in the System Design Guide .
2. The SLEEP# pin should be driven by the proper signal on the southbridge:
•
ALI 1535: an AND gate whose inputs are SUSPEND# (pin W13) and AGP_STP# (pin
E11). The AND gate must have 5 V tolerant inputs and a 3.3 V output.
• The processor Reserved pin G2 should control the unprotect feature of the parallel
ROM.
3. If a unified ROM (i.e. Code Morphing software and BIOS in a parallel ROM) is supported:
•
EPROMA[2:1] should connect to the highest order address lines on the parallel ROM.
• The processor’s GPIO should switch 12 V onto the parallel ROM.
4. The Maxim thermal sensor should be connected as follows:
•
MAX1617 pin 3 to processor pin A18.
• MAX1617 pin 4 to processor pin B16.
• MAX1617 alert output to THERM# input of ALI 1535.
• If a MAX1619 is supported, the OVERH# output should not be used.
5. The free running PCI clock (PCICLK_F) should connect to the processor’s PCI clock input
as well as the southbridge PCI clock input. Since most clock generators have only one
free running PCI clock, special routing considerations are necessary. See also Chapter 6,
Using CLKRUN in the System Design Guide .
6. The RESET# pin on the Transmeta debug connector must be connected to reset only the
processor. The SYS_RST# pin on the Transmeta debug connector should be connected
in such a manner as to reset the entire system when asserted.
All processor reset pins should be connected as shown in the Chapter 6,
System Reset , in
the System Design Guide.