Transmeta Crusoe TM5500, System Design Manual

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July 17, 2002
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C h a p t e r 7
PCB Layout Guidelines
7.1 PCB Design Layout
• For thermal sensor/diode signal routing make sure to follow the guidelines in Thermal Diode and Thermal
Sensor on page 103 .
• V_CPU_CORE is placed on the bottom layer (Signal 4). All other supply voltages are placed on the PWR
layer. If possible, place a V_CPU_CORE plane on as many layers as possible.
• GND 1 is the signal return path for traces on Signal 1 and 2. GND 1 plane is to be solid, with no breaks or
cuts.
• GND 3 is the signal return path for traces on Signal 3 and 4 (6 and 5 for ten layer stack-ups). The GND 1,
GND2, and GND 3 Planes are to be solid, with no breaks or cuts.
• Anti-pad treatment for vias on GND 1, GND 2, GND 3, and PWR layers. Pad diameter is to be smaller
than the via hole. With 0.007" to 0.008" clearance from the via hole to the plane. This results in 0.022" to
0.023" copper between vias under the processor. If normal anti-pad treatments were allowed, the amount
of copper under the chip would be severely decreased, limiting processor performance.
• Material between PWR and GND 2 layers must be a maximum of 0.005" thick. Thinner is desirable
(0.003” should be attainable).
• If the previous note is followed, signals run on Signal 2 (Inner Layer 3) may cross cuts or breaks on the
PWR plane (Inner Layer 4). Critical signals may also then be placed on any signal layer.
• HCLK and PCI_CLK to the processor should have matched lengths. Also, each PCI device/slot clock
should be matched to this same length.
• All vias on the pad side of the PCB processor BGA footprint must be covered with solder mask. Failure to
do so will potentially short signals together during the soldering process.
• Keep trace lengths as short as possible.
Note
The guidelines in this chapter must be followed for the design to meet specified TM5500/TM5800 processor
operating frequencies.