Transmeta Crusoe TM5500, System Design Manual

Page: 36 / 130

July 17, 2002
36
Processor Power Supplies and Power
Management
Under the above startup conditions the processor VDRA signals (that go to the VRM VID inputs) are not valid
until the processor I/O voltages are present. Therefore, another method must be provided to supply valid VID
signals to the VRM from the time the V_CPU_CORE core supply is enabled to the time the processor I/O
voltages are within specifications. Once the processor I/O voltages are valid, the processor-suppled VDRA
signals are valid and can be used to control the V_CPU_CORE core supply voltage.
When using TM5500/TM5800 processors with existing TM5400/TM5600 system designs, the existing power
supply sequencing should not be used unless it meets the TM5500/TM5800 sequencing requirements
described above, due to the likelihood for current surges on the I/O power supplies if the I/O voltages are
applied to the processor prior to the V_CPU_CORE core supply reaching V_CPU_CORE
MIN
.
With the previously recommended TM5400/TM5600 power supply circuit, a high current on the I/O power
supply circuits has been observed for about 3-10 ms, and its magnitude can be up to the current limit of the
particular 3.3 V or 2.5 V regulator used (testing has shown up to 3.5 A). The excess current is not due to I/O
contention, but rather current flow through the power supply pins of the processor.
This could possibly have the following negative effects for the system:
• DDR SDRAM data corruption when exiting STR (suspend-to-RAM).
• The 2.5 V or 3.3 V regulator may go into under-voltage shutdown or over-current protection, in which
case system operation may only be recoverable if power-cycled.
• The 2.5 V or 3.3 V supply voltage may dip enough to cause memory corruption and power supply latch-
off.
• The current spike may trigger other system-level protection circuits or result in I/O contention.
3.2.2 Power Sequencing Circuit Examples
As explained above in Power Sequencing Requirements on page 35, TM5500/TM5800 processors must
have the core voltage (V_CPU_CORE) turned on prior to the I/O voltages (V3_3 and V2_5). However, the
processor VRDA output code presented to the VRM VID inputs is not valid until the I/O voltages reach
regulation. The processor core VRM must rely on another method for setting the VRM output voltage during
processor power-up.
The fundamental requirement is to force the processor core VRM to a fixed startup supply voltage by a means
other than the VID inputs, and then use the VRDA outputs from the processor to control the core VRM output
only when these VRDA signals are valid.
The processor core VRM designs shown in this document each have the ability to force the startup supply
voltage (FORCE_STARTUP_V) without having a valid VID input code available from the processor. Two
methods for using this capability are provided in the power supply sequencing reference design schematics
below. Only one method is necessary for any system design, at the option of the designer. These two
methods are described below:
Method 1 (Delay): This method uses a delay to drive the FORCE_STARTUP_V signal long enough for the
I/O voltages to reach regulation. The advantage of this solution is lower cost and fewer components than
Method 2.
Method 2 (Monitor): This method measures the I/O voltages to insure they are in regulation before releasing
the FORCE_STARTUP_V signal. The advantage of this method over Method 1 is that it relies on actual
voltage levels for control and is not susceptible to potential delay timing variability issues.
Power Supply Sequencing Reference Design Schematic
Two possible power supply sequencing circuits, as described above, are shown in the reference design
schematic on the following page.