Transmeta Crusoe TM5500, System Design Manual

Page: 119 / 130

July 17, 2002
119
System Design Checklists
11. If DDR memory is supported, the decoupling on 2.5 V STR at the DRAMs should be:
•
High frequency: approximately 3 low-ESL ceramic capacitors as close as possible to
the power pins of each DRAM. Recommended value is 0.1 µF with 0603 case size
and X7R dielectric.
• Mid frequency: none required.
• Low frequency: one 10 µF capacitor for approximately every 2 DRAMs. Each
capacitor should be either ceramic or low-ESR tantalum.
12. Ensure that PLLVDD tracking circuit has been incorporated.
DRAM Checklist
Item Description Status
1. Designs with no DDR should connect the high-order SDR chip selects to the most
permanent bank of memory. That is, CS[3:2], CLK[3:2], and CKE1 should connect to the
most permanent banks of SDR.
2. The CKE high-speed bidirectional level-translator should be:
•
Controlled by SUS_STAT1# (pin T17) on the iPIIX4 or SUSPEND# (pin W13) on the
ALI 1535 .
• Controlled by the same signal that is connected to the processor SLEEP# pin.
• Powered by at least 4.3 V. If less than 4.3 V is used, the signals will be clamped, and
noise margin will be reduced.
3. There can be no more than 8 DDR devices.
4. DDR and SDR x32 memory is not supported.
SDR SDRAM Address Line Connections
1
Processor Signal
DRAM
Signal JEDEC SODIMM-144
Pin Number JEDEC DIMM-168
Pin Number
Name Pin Number
S_A[0] P3 A0 29 33
S_A[1] N4 A1 31 117
S_A[2] V5 A2 33 34
S_A[3] P4 A3 30 118
S_A[4] N5 A4 32 35
S_A[5] M1 A5 34 119
S_A[6] P1 A6 103 36
S_A[7] N1 A7 104 120
S_A[8] P2 A8 105 37
S_A[9] N2 A9 109 121
S_A[10] M2 A10 / AP 111 38
S_A[11] K1 A11 112 123
S_A[12] K2 A12 70 126
S_BA[0] L2 BA0 106 122
S_BA[1] L1 BA1 110 39
1. Designs containing an SDR SODIMM should connect the address lines as shown in this table.
Power Supply Checklist
Item Description Status