Transmeta Crusoe TM5500, System Design Manual

Page: 87 / 130

July 17, 2002
87
System Design Considerations
6.3 Signal Pull-ups and Pull-downs
The following signals should be pulled up to V2_5: IGNNE#, INTR, INIT#, NMI, FERR#, and SMI#.
During the Deep Sleep power management state, the processor clock is stopped and most I/O pins are tri-
stated (see the ACPI specification). Care must be taken to ensure that all signals going to sections of the
system that are powered on during suspend must be pulled up/down to a valid state when the processor tri-
states its outputs.
Specifically, PCI_GNT# and other PCI control signals are most important, so that the PCI agent is not
confused when the grant lines float low.
TM5500/TM5800 processor signals should be pulled up or down as shown in the table below. Many of these
signals are outputs from the processor, and all non-DRAM processor outputs are tri-stated (float) during Deep
Sleep.
Table 15: Signal Pull-up/Pull-down Requirements
Processor Signal
Pull-up / Pull-down Resistor
Value / Configuration
Name Pin Number Type
FERR# H16 Output 10 K
Ω
pull-up to V2_5
IGNNE# H15 Input
INIT# G18 Input
INTR G19 Input
NMI H17 Input
SMI# G14 Input
STPCLK# H18 Input
EPROMA[0] J16 Output None (test point only)
EPROMA[1] J15 Outputs 10 K
Ω
pull-up to V3_3
EPROMA[2] J19 Output
P_CLKRUN# J18 Bidirectional
P_GNT#[0] G15 Output
P_GNT#[1] A16 Output
P_GNT#[2] F13 Output
P_GNT#[3] A15 Output
P_GNT#[4] G16 Output
P_GNT#[5] F17 Output
P_HOLDA# E13 Output
SROM_CS#[0] K15 Output
SROM_CS#[1]
1 L15 Output
TCK W7 Input
SROM_SCLK L16 Output 10 K
Ω
pull-up to V3_3 -or-
10 K
Ω
pull-down to ground
SROM_SOUT K18 Output
CFG_SDATA A8 Bidirectional 1.2 K
Ω
pull-up to V3_3 -or-
4.7 K
Ω
pull-down to ground
2