Transmeta Crusoe TM5500, System Design Manual

Page: 26 / 130

July 17, 2002
26
Processor Power Supplies and Power
Management
Startup Mode
Startup mode is selected when the ZMODE signal is high. In this mode the output voltage is determined by
the internal impedance mode resister whose value is set on the rising edge of the ZMODE signal. The device
looks at the impedance on the VID inputs. If it is > 90 K
Ω
it is considered a logic high, and if it is < 1.1 K
Ω
it is
considered a logic low. This process is initiated by the rising edge of the ZMODE signal. During this time the
device tries to move its VID inputs by alternately trying to pull the VID inputs high with a pull-up resistor to 5 V,
and low through a pull-down resistor to ground. This happens over the period of a few µS. To make the VID
input a logic 1 (high), insert a 100 K
Ω
resistor in series with the VID input. To make the VID input a logic 0
(low), make the series resistor zero
Ω
. In addition to the series resistors, a pull-up resistor of 1 K
Ω
must be
added to each VID input. If pull-up resistors of > 1 K
Ω
are used to limit supply current, then a 4.7 nF capacitor
must be added across each pull-up resistor to keep the AC impedance < 1 K
Ω
.
Deep Sleep Extension (DSX) Mode
The MAX1718 VRM supports a Deep Sleep extension (DSX) mode that can provide a very low output voltage
to the TM5500/TM5800 processor core during extended Deep Sleep periods, significantly reducing processor
leakage power during long intervals of sustained system inactivity. The reference design example provided at
the end of this section shows the DSX mode configured for 0.9 V operation. This can be reconfigured to a
lower TM5500/TM5800 DSX voltage specification when it becomes available. See Table 9 for DSX voltage
programming information.
Driving the SUS signal high overrides the ZMODE control and sets the output voltage to one of thirteen preset
values between 0.600 V and 0.900 V, depending on the state of the S0 and S1 inputs. The S0 and S1 inputs
are each effectively quad-state / four-level logic, and can be set by connecting them to either the VRM VCC
(+5 V), REF, or GND signals, or leaving the input open. Since each input has four states and there are two
inputs, there are 2
4
= 16 possible combinations, of which only thirteen are used here.
The table below provides DSX mode output voltage configuration information for the full range of DSX
voltages.
Note
Although this feature is incorporated in the MAX1718 VRM, it is not yet qualified for the TM5500/TM5800
processor.
Table 9: MAX1718 DSX Voltage Configuration
DSX Voltage S0 S1
0.900 V VCC GND
0.875 V GND REF
0.850 V REF REF
0.825 V OPEN REF
0.800 V VCC REF
0.775 V GND OPEN
0.750 V REF OPEN
0.725 V OPEN OPEN
0.700 V VCC OPEN
0.675 V GND VCC
0.650 V REF VCC
0.625 V OPEN VCC
0.600 V VCC VCC