Transmeta Crusoe TM5500, System Design Manual

Page: 69 / 130

July 17, 2002
69
SDR Memory Design
5.3.3 Write Timing
The minimum output hold time of the processor exceeds the input hold time of the SDRAM by:
Because of this, the flight time of the clock must not exceed the latest data, address or control signal by more
than 450 pS. Unfortunately, compensation must be made for the negative skew built into the JEDEC
specification.
The clock length on an SODIMM is specified as 2.50”, or 445 pS (routed on inner traces). All the other signals
on the SODIMM are some distance less than this. This difference must be added to each trace on the
motherboard as timing compensation, as specified in Table 14 below.
As an example of this required timing compensation, the data lines on the motherboard must all be at least
353 pS longer than the clocks.
This rule ensures that the maximum capacitive loading on each driver does not exceed the driver’s specified
capacity.
It is important to note that this restriction is an original design limitation. The system may well be capable of
successfully driving a longer line. However, Transmeta has not simulated this or designed for it, so violating
this rule is done at the designer's risk.
Finally, the clocks traces must be as short as possible. This minimizes potential EMI and signal integrity
problems.
Critical Rule
A design can have no more than 450 pS of negative skew between the clock (at the SDR SDRAM) and all
other inputs.
1.25 nS – 0.80 nS = 0.45 nS
Table 14: Write Timing Compensation
Signal Group Minimum Length Delay as Outer Trace
Delay Added to
Motherboard
Data 0.60” 92 pS 353 pS
Data Mask 1.00” 153 pS 292 pS
Address/Control 0.75” 115 pS 330 pS
Select 1.00” 153 pS 292 pS
Clock Enable 1.00” 153 pS 292 pS
Critical Rule
If 16 SDRAMS are used, the longest trace cannot be more than 5” in length, including the trace on the
SODIMM. If the number of SDRAM chips is limited to 12, this maximum trace length can be increased to 8”.