TR5-Lite User Manual
59
June 20, 2018
The value of OUTPUT DIVIDER can be specified by the OD0, OD1 and OD2 control pins
according to the following table:
After specifying the desired output frequency in the parallel interface, developers must assert the
output enable pin CE and control the RSTN pin to generate a rising signal to start the PLL
Recalibration process. In the TR5-Lite, the required output type is LVDS, so always set OS0 and
SO1 to 0 and 1, respectively.
5
5
.
.
2
2
S
S
i
i
5
5
7
7
0
0
E
E
x
x
a
a
m
m
p
p
l
l
e
e
b
b
y
y
R
R
T
T
L
L
In this section we will demonstrate how to use the Terasic SI570 Controller implemented in Verilog
to control the SI570 programmable oscillator on the TR5-Lite board. This controller IP can
configure the SI570 to output a clock with a specific frequency via I2C interface. For demonstration,
the output clock is used to implement a counter where the MSB is used to drive an LED, so the user
can get the result from the frequency of the LED blinking. We will also introduce the port
declarations and associated parameter settings of this IP.
shows the block diagram of this
demonstration.
