Terasic TR-5 Lite FPGA, User Manual

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TR5-Lite User Manual 21 www.terasic.com
June 20, 2018
Table 2-8 lists the clock source, signal names, default frequency and their corresponding Stratix V
GX device pin numbers.
Table 2-8 Clock Source, Signal Name, Default Frequency, Pin Assignments and Functions
Source
Schematic
Signal Name
Default
Frequency
I/O Standard
Stratix V GX Pin
Number
Application
Y2
OSC_50_B3B
50.0 MHz
2.5-V PIN_AW35
OSC_50_B3D 2.5-V PIN_BC28
OSC_50_B4A 1.5-V PIN_AP10
OSC_50_B4D 1.5-V PIN_AY18
OSC_50_B7A 1.8-V PIN_M9
OSC_50_B7D 1.8-V PIN_J18
OSC_50_B8A 1.8-V PIN_R36
OSC_50_B8D 1.8-V PIN_R25
U2 SFP_REFCLK _p 100.0 MHz LVDS PIN_AK7 10G SFP+
U46 SFP1G_REFCLK_p 100.0 MHz LVDS PIN_AH6 1G SFP+
U46 SATA_REFCLK_p 100.0 MHz LVDS PIN_AF7 SATA
J4 PCIE_REFCLK_p From Host LVDS PIN_AK38 PCI Express
2
2
.
.
6
6
R
R
S
S
-
-
4
4
2
2
2
2
S
S
e
e
r
r
i
i
a
a
l
l
P
P
o
o
r
r
t
t
The RS422 is designed to perform communication between boards, allowing a transmission speed
of up to 20 Mbps. Figure 2-7 shows the RS-422 block diagram of the development board. The
full-duplex LTC28255 is used to translate the RS-422 signal, and the 1394 is used as an external
connector for the RS-422 signal.