Terasic TR-5 Lite FPGA, User Manual

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TR5-Lite User Manual 82 www.terasic.com
June 20, 2018
Chapter 7
Transceiver Verification
This chapter describes how to verify the FPGA transceivers using the test code provided in the
DE5-Net system CD.
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The transceiver test code verifies the transceiver channels through an external loopback method.
The following transceiver channels can be verified with different data rates:

10.3125 Gbps: SPF-A, SPF-B

6.0 Gbps: SATA Host

8.0 Gbps: PCIe Channel 0~7
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To enable an external loopback of transceiver channels, specific loopback fixtures are required.
Some fixtures may be proprietary to Terasic.
For SFP+ loopback, optical SFP+ loopback fixtures are required. Figure 7-1 shows the optical
SFP+ loopback fixture.
Figure 7-1 Optical SFP+ Loopback Fixture