TR5-Lite User Manual
5
June 20, 2018
FPGA
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Altera Stratix® V GX FPGA (5SGXEA7N2F45C2)
FPGA Configuration
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JTAG header for FPGA programming
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Fast passive parallel (FPPx32) configuration via MAX II CPLD and flash memory
General user input/output:
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4 LEDs
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2 push-buttons
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2-position DIP switch
On-Board Clock
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50MHz Oscillator
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Programmable oscillators Si570 and CDCM61004
Memory
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DDR3 SDRAM
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QDRII+ SRAM
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FLASH
Communication Ports
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Two SFP+ connectors
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One Serial ATA (SATA II) host port
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PCI Express (PCIe) x8 edge connector
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One RS422 transevier with 1394 connector
System Monitor and Control
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Temperature sensor
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Fan control
Power
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PCI Express 6-pin power connector, 12V DC Input
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PCI Express edge connector power
