TR5-Lite User Manual
46
June 20, 2018
enable or disable a component according to their design by simply marking a check or removing the
check in the field provided. If the component is enabled, the TR5-Lite System Builder will
automatically generate the associated pin assignments including the pin name, pin location, pin
direction, and I/O standards.
Note. The pin assignments for some components for e.g. DDR3 and SFP+ require associated
controller codes in the Quartus project otherwise Quartus will result in compilation errors.
Therefore, do not select them if they are not necessary in your design. To use the DDR3 controller,
please refer to the DDR3 SDRAM demonstration in Chapter 6.
Figure 3-4 System Configuration Group
Programmable Oscillator
There are two external oscillators on-board that provide reference clocks for the following signals
SFP_REFCLK, SFP1G_REFCLK and SATA_REFCLK. To use these oscillators, users can select
the desired frequency on the Programmable Oscillator group, as show in
. SPF+ or SATA
should be checked before users can start to specify the desired frequency in the Programmable
Oscillator group.
As the Quartus project is created, System Builder automatically generates the associated controller
according to users’ desired frequency in verilog which facilitates users’ implementation as no
additional control code is required to configure the programmable oscillator.
Note. If users need to dynamically change the frequency, they would need to modify the generated
