TR5-Lite User Manual
20
June 20, 2018
TEMPDIODEn
Negative pin of temperature diode in
Stratix V
2.5-V
PIN_EP7
TEMP_CLK
SMBus clock
2.5-V
PIN_F35
TEMP_DATAT
SMBus data
2.5-V
PIN_E35
TEMP_OVERT_n
SMBus alert (interrupt)
2.5-V
PIN_H35
TEMP_INT_n
SMBus alert (interrupt)
2.5-V
PIN_G34
FAN_CTRL
Fan control
2.5-V
PIN_F34
2
2
.
.
5
5
C
C
l
l
o
o
c
c
k
k
C
C
i
i
r
r
c
c
u
u
i
i
t
t
The development board includes one 50 MHz and two programmable oscillators.
the default frequencies of on-board all external clocks going to the Stratix V GX FPGA. The figures
also show an off-board external clock from PCI Express Host to the FPGA.
Figure 2-6 Clock circuit of the TR5-Lite
A clock buffer is used to duplicate the 50 MHz oscillator, so each bank of FPGA I/O bank 3/4/7/8
has two clock inputs. The two programming oscillators are low-jitter oscillators which are used to
provide special and high quality clock signals for high-speed transceivers.
