TR5-Lite User Manual
4
June 20, 2018
Chapter 1
Overview
This chapter provides an overview of the TR5-Lite Development Board and installation guide.
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The Terasic TR5-Lite Stratix V GX FPGA Development Kit provides the ideal hardware solution
for designs that demand high bandwidth, advanced memory interfacing, and power efficiency in a
convenient half-height, half-length form-factor package. Designed for the most demanding high-end
applications, the TR5-Lite is empowered with the top-of-the-line Altera Stratix V GX, delivering
the best system-level integration and flexibility in the industry.
The Stratix® V GX FPGA features integrated transceivers that transfer at a maximum of 12.5 Gbps,
allowing the TR5-Lite to be fully compliant with version 3.0 of the PCI Express standard, as well as
allowing an ultra low-latency, straight connections to dual external 10G SFP+ modules. Not relying
on an external PHY will accelerate mainstream development of network applications enabling
customers to deploy designs for a broad range of high-speed connectivity applications. Matched
with two independent banks of DDR3 RAM, four independent banks of QDRII, and flash memory,
the TR5-Lite fully delivers in all high-bandwidth applications such as high frequency trading, data
acquisition, network processing, and signal processing.
It is highly recommended that users read the
TR5-Lite
Getting Started Guide
before using the
TR5-Lite board.
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The following hardware is implemented on the TR5-Lite board:
