Terasic TR-5 Lite FPGA, User Manual

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TR5-Lite User Manual 36 www.terasic.com
June 20, 2018
QDRIID_Q5 Read Data bus[5] 1.8-V HSTL Class I PIN_Y30
QDRIID_Q6 Read Data bus[6] 1.8-V HSTL Class I PIN_Y29
QDRIID_Q7 Read Data bus[7] 1.8-V HSTL Class I PIN_U29
QDRIID_Q8 Read Data bus[8] 1.8-V HSTL Class I PIN_V30
QDRIID_Q9 Read Data bus[9] 1.8-V HSTL Class I PIN_C30
QDRIID_Q10 Read Data bus[10] 1.8-V HSTL Class I PIN_Y27
QDRIID_Q11 Read Data bus[11] 1.8-V HSTL Class I PIN_D30
QDRIID_Q12 Read Data bus[12] 1.8-V HSTL Class I PIN_Y28
QDRIID_Q13 Read Data bus[13] 1.8-V HSTL Class I PIN_W28
QDRIID_Q14 Read Data bus[14] 1.8-V HSTL Class I PIN_V28
QDRIID_Q15 Read Data bus[15] 1.8-V HSTL Class I PIN_B31
QDRIID_Q16 Read Data bus[16] 1.8-V HSTL Class I PIN_A31
QDRIID_Q17 Read Data bus[17] 1.8-V HSTL Class I PIN_A32
QDRIID_BWS_n0 Byte Write select[0] 1.8-V HSTL Class I PIN_T31
QDRIID_BWS_n1 Byte Write select[1] 1.8-V HSTL Class I PIN_R30
QDRIID_K_p
Clock P
Differential 1.8-V HSTL Class I PIN_K30
QDRIID_K_n
Clock N
Differential 1.8-V HSTL Class I PIN_K29
QDRIID_CQ_p Echo clock P 1.8-V HSTL Class I PIN_T28
QDRIID_CQ_n
Echo clock N
1.8-V HSTL Class I PIN_C31
QDRIID_RPS_n
Report Select
1.8-V HSTL Class I PIN_U30
QDRIID_WPS_n
Write Port Select
1.8-V HSTL Class I PIN_P30
QDRIID_DOFF_n PLL Turn Off 1.8-V HSTL Class I PIN_G31
QDRIID_ODT
On-Die Termination
Input
1.8-V HSTL Class I PIN_D32
QDRIID_QVLD Valid Output Indicator 1.8-V HSTL Class I PIN_E32