TR5-Lite User Manual
79
June 20, 2018
Figure 6-3
Block diagram of the DDR3 Basic Demonstration
The system flow is controlled by a Nios II program. First, the Nios II program writes test patterns
into the whole 1 GB of SDRAM. Then, it calls Nios II system function, alt_dache_flush_all, to
make sure all data has been written to SDRAM. Finally, it reads data from SDRAM for data
verification. The program will show progress in JTAG-Terminal when writing/reading data to/from
the SDRAM. When verification process is completed, the result is displayed in the JTAG-Terminal.
Altera DDR3 SDRAM Controller with UniPHY
To use Altera DDR3 controller, users need to perform the four major steps:
1.
Create correct pin assignments for DDR3.
2.
Setup correct parameters in DDR3 controller dialog.
3.
Perform “Analysis and Synthesis” by clicking Quartus menu: Process
Start
Start
Analysis & Synthesis.
4.
Run the TCL files generated by DDR3 IP by clicking Quartus menu: Tools
TCL Scripts…
