Terasic TR-5 Lite FPGA, User Manual

Page: 17 / 86

TR5-Lite User Manual 17 www.terasic.com
June 20, 2018
Figure 2-4 Position Dip Switch for FPGA Configuration
Table 2-3 SW1 FPGA Configuration Settings
Board
Reference
Description Default
SW1
On : User-defined Configuration
Off: Factory Default Configuration
Off
2
2
.
.
3
3
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G
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I
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/
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O
O
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This section describes the user I/O interface to the FPGA.

User Defined Push-buttons
The TR5-Lite board includes two user defined push-buttons that allow users to interact with the
Stratix V GX device. Each push-button provides a high logic level or a low logic level when it is
not pressed or pressed, respectively. Table 2-4 lists the board references, signal names and their
corresponding Stratix V GX device pin numbers.